Basic Computer Organisation Questions and Answers

Answer: A

They are stored as 00000101B and 00110101B.

The number 5 is stored in pure binary: \(5 = 101_2\), which in a byte is 00000101. The character '5' is stored as its ASCII code, 35H = 53 decimal, which is 00110101 in binary.

Option C's 00000011 is 3, not 5, and option B's 01110101C is not a valid binary byte. So only option A is right, and 'None of the above' is wrong.

Answer: C

The answer is 4 and 3.

Taking the 8085 as the standard example, the opcode fetch machine cycle takes four T-states: three to place the address, read the opcode from memory and latch it, and a fourth in which the processor decodes it. A memory read or write machine cycle in the execution phase takes three T-states, since no decoding is needed.

So an instruction such as MVI A, data takes 4 T-states to fetch the opcode and 3 more to read the data byte. The option '3 and 4' reverses the two, and 2 and 1, or 2 and 3, are too few for either cycle.

Answer: C

The table is the exclusive OR, \(F \leftarrow A \oplus B\).

F is 1 exactly when A and B differ (01 and 10) and 0 when they are equal (00 and 11). That is the XOR micro-operation.

AND would give 1 only for 11. NAND would give 1 for 00, 01 and 10. XNOR, the complement of XOR, would give 1 for 00 and 11, the opposite of the table.

Answer: A

R1 ← R2 means load the content of R2 into R1.

In register transfer language the arrow shows a transfer: the contents of the source register on the right are copied into the destination register on the left. The transfer is non-destructive, so R2 keeps its value.

Addition would be written R1 ← R1 + R2. Nothing in the statement clears R2, so the two options that delete its contents describe a different operation.

Answer: C

Instruction decode determines the opcode and operands of the instruction.

After the fetch phase has brought the instruction into the instruction register, the control unit decodes it: it interprets the opcode to find which operation is required and works out the operands and addressing mode, so the right control signals can be generated.

Loading the instruction into the CPU is the fetch phase. The instruction is already in machine code, so nothing is translated at this stage; translation from source to machine code is done earlier by a compiler or assembler. Carrying out the operation is the execute phase.

Answer: C

The correct sequence is load instruction address, get the instruction, get effective address of operands, execute the opcode.

The instruction cycle starts by placing the program counter's address on the bus, then fetches the instruction from memory. Once it is decoded, the CPU computes the effective addresses of its operands (fetching them if they are in memory), and only then executes the operation.

The other sequences are impossible: the CPU cannot work out operand addresses before it has fetched the instruction that names them, and it cannot execute before it has its operands.