Computer Network Questions and Answers

Answer: D

Correct answer: Shift register

A shift register is sequential, because it is built from flip-flops and its output depends on the bits already stored as well as on the present input. The other three are combinational: their outputs are determined entirely by their present inputs, with no memory of what came before. Each can be fully specified by a truth table. The dividing line is memory. Combinational circuits include adders, multiplexers, demultiplexers, decoders, encoders, comparators and code converters. Sequential circuits include flip-flops, latches, registers, shift registers and counters, and they need a clock. Sequential circuits are described by state tables and state diagrams, and they divide further into synchronous designs, where every element is clocked together, and asynchronous ones, where changes propagate as they occur. Every sequential circuit contains combinational logic inside it, generating the next state and the outputs, so the two categories are layered rather than opposed.

Answer: A

Correct answer: True

The statement is true. The 1’s complement simply changes each 0 to 1 and each 1 to 0, and in hardware it is a row of inverters. The 2’s complement goes one step further: invert every bit and then add 1. That extra step is what makes it the representation actually used for signed integers. The reason for preferring it is practical. 2’s complement has a single representation of zero, whereas 1’s complement has two - 00000000 and 11111111 - which complicates comparison. And 2’s complement addition needs no end-around carry: the same adder handles signed and unsigned values, so subtraction becomes addition of the complement and no separate subtractor is required. In eight bits, 2’s complement covers −128 to +127, the asymmetry arising from that single zero. 1’s complement is still met in checksum calculations, notably in the Internet protocols.

Answer: B

Correct answer: AND gate

The rules describe an output that is HIGH only when both inputs are HIGH and LOW in every other case, which is the AND function. An OR gate would be HIGH whenever either input was HIGH.

Answer: C

Correct answer: 10 base T

10Base-T runs twisted pair from each station to a central hub, which is a physical star. 10Base5 and 10Base2 are coaxial buses.

Answer: B

Correct answer: XOR gate

A half adder adds two bits and produces SUM = A ⊕ B from an XOR gate, while CARRY = A · B comes from an AND gate. XOR is the right choice because the sum bit is 1 exactly when the two inputs differ.

Answer: B

Correct answer: A + AB = A

The absorption law states A + AB = A, because whenever AB is true A is already true, so the second term adds nothing. It is one of the most useful simplifications when reducing an expression by hand.

Answer: B

Correct answer: Link state

In a link state protocol every router floods a description of its own links to all the others, so each ends with the same map of the network and computes its own shortest paths from it. Distance vector routers exchange only their own distance tables and never share a common database.

Answer: A

Correct answer: Hot potato routing

Hot potato routing sends each packet out on whichever queue is shortest, getting rid of it as fast as possible without regard to where it is going. Flooding sends copies everywhere, and static routing consults a fixed table.

Answer: B

Correct answer: time-division

A time-division switch works by writing incoming samples into memory and reading them out in a different order, so each sample must be stored and fetched again. That store-and-fetch is the source of the delay; a space-division crossbar makes a direct path and adds none.

Answer: B

Correct answer: Entropy

Entropy measures the average uncertainty of a source: the more evenly spread its symbol probabilities, the more information each symbol carries. Bandwidth measures the channel, not the source.