Communication Protocols in Embedded Systems Questions and Answers

Answer: A

Correct answer: 1-Q, 2-R, 3-P

Three buses, three quite different designs. I2C is two shared wires with addressing in the protocol and an acknowledgement per byte. SPI is full duplex with a separate select line for each device and no addressing at all. CAN uses a differential pair with non-destructive arbitration, so the highest-priority message wins the bus without any message being lost or corrupted.

Answer: B

Correct answer: 1-Q, 2-R, 3-P

Each transfer type matches a different requirement. Interrupt transfers poll at a guaranteed interval with a small payload, which suits a keyboard or mouse. Bulk transfers use whatever bandwidth is left and retry until correct, which suits mass storage. Isochronous transfers reserve bandwidth and never retry, which suits audio.

Answer: C

Correct answer: 1 and 2 only are correct

Statements 1 and 2 are correct: the lines are open-drain, so pull-up resistors are essential and their value sets the rise time and hence the maximum speed; and the bus supports multiple masters with arbitration. Statement 3 is wrong - I2C is single-ended, which is why its reach is measured in centimetres rather than metres.

Answer: D

Correct answer: 2, 1, 4, 3

Arbitration comes first, on the identifier, so the bus is resolved before any data is sent - and because it is non-destructive the winning frame proceeds uninterrupted. The data field follows, then the CRC covering everything transmitted so far, and finally the acknowledgement slot in which any node that received the frame correctly asserts a dominant bit. The acknowledgement must come after the CRC, since it certifies it.

Answer: A

Both are limited by cable length in much the same way and RS-485 can run faster over short distances. CAN's advantages lie in the arbitration, the error handling and the message priority, all of which Modbus leaves to the software.

Answer: B

Correct answer: both sensors responding to the same fixed address

I2C selects a device by address, so two identical parts with the same fixed address both answer at once and corrupt the data and acknowledgement. The usual remedies are a part with address-select pins, a second I2C bus, or an I2C multiplexer. Bus capacitance and acknowledgement timing are real problems on longer buses but would not appear as a clean failure on adding a second identical device.

Answer: C

A percentage error that is tolerable at a low rate is often generated by a divider that cannot express the higher rate exactly, particularly from an untrimmed internal oscillator. A parity mismatch would fail at both speeds and a small buffer gives overruns rather than framing errors.

Answer: D

SPI genuinely has no error detection, and the clock is indeed supplied with the data, but the second fact does not make errors impossible: a noisy or overlong link corrupts data whatever carries the clock. Any checking has to be added by the application.

Answer: A

Because a zero overrides a one during arbitration, the numerically lower identifier always wins, so allocating the identifiers is allocating the priorities. It is the reason identifier assignment is a design activity rather than an arbitrary labelling.

Answer: B

SPI is synchronous and the master's clock accompanies every bit, which is why there is no baud rate to agree. The other three recover timing from the data itself, which is what makes a rate mismatch possible on all of them.