Combinational CMOS Logic Design Questions and Answers

Answer: B

The p-MOS transistors act as the pull-up network.

A CMOS gate has a pull-up network of p-MOS transistors between V_DD and the output and a complementary pull-down network of n-MOS transistors between the output and ground. A p-MOS transistor conducts when its gate is low and passes a strong logic 1, so it is used to pull the output up to V_DD; the n-MOS network passes a strong 0 and pulls it down.

The pull-down role belongs to the n-MOS transistors. In a properly designed CMOS gate neither network is a short to ground or a passive load; the p-MOS 'load' belongs to older pseudo-nMOS logic.

Answer: C

The circuit is a two input CMOS NOR gate.

The output X is pulled up to V_DD only through two p-MOS transistors in series, so it goes high only when both are on, that is, when A and B are both 0. The two n-MOS transistors in parallel pull X down to V_SS whenever either A or B is 1. The output is therefore 1 only for A = B = 0:

\[ X = \overline{A + B} \]

A NAND gate has the opposite arrangement, p-MOS in parallel and n-MOS in series. AND and OR gates need an extra inverter stage after the NAND or NOR, which this single-stage circuit does not have.