IO Organisation and Interrupts Questions and Answers

Answer: D

Asynchronous buses use handshaking because devices have unpredictable response time.

An asynchronous bus has no common clock. Instead, the master raises a request signal and waits until the slave raises an acknowledge signal, then each side drops its signal in turn. Every transfer therefore takes exactly as long as the responding device needs, which is what lets fast processors and slow or variable-speed devices (memory, I/O controllers) share one bus.

Clock skew is a problem for long synchronous buses and one reason to avoid a clock, but the handshake itself exists to cope with varying response times. If access time were constant, a synchronous bus with fixed timing would do the job. Cache controllers do not require handshaking.

Answer: D

The one that is not an 8085 interrupt is MCLR.

The 8085 has five hardware interrupts: TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR. MCLR is the master clear (reset) pin of some microcontrollers such as Microchip's PIC, not an 8085 interrupt.

RST 7.5, INTR and RST 5.5 are all genuine 8085 interrupt inputs.

Of the 8085 interrupts, TRAP is the only non-maskable one, and RST 7.5, 6.5 and 5.5 are vectored to fixed addresses.

Answer: A

The technique is daisy chaining.

In daisy chaining the bus-grant line runs through the devices one after another. The grant reaches the device nearest the processor first, and if that device is requesting it keeps the grant and does not pass it on. Priority is therefore fixed by physical position, with the closest device highest.

In polling the controller asks each device in turn, and the order can be changed in software. With independent requesting each device has its own request and grant lines, and priority is decided by the arbiter. A time-slice method shares the bus in turns rather than by position.

Answer: D

Interrupts initiated by an instruction are software interrupts.

A program executes an instruction, such as INT in the 8086 family or a system call, that causes an interrupt on purpose, for instance to ask the operating system for a service. Hardware interrupts (C) come from devices and are external events (B) signalled to the processor. 'Internal' (A) interrupts, or traps, arise from conditions such as division by zero inside the processor.

Answer: C

A CPU does not break off an instruction in the middle. It checks for pending interrupts at the end of the current instruction, and then runs the interrupt service routine. So it handles an interrupt by checking the interrupt register after finishing the execution of the current instruction, option (C). Acting as soon as the interrupt is raised would split the instruction, checking only at the end of the fetch cycle is too early, and checking at fixed time intervals is polling, not the usual hardware mechanism.

Answer: A

The 8251 is the USART, the universal synchronous and asynchronous receiver transmitter, used for serial communication (a). The 8051 is a microcontroller, with a processor, memory and ports in one chip (b). The 8259 is the programmable interrupt controller (c), and the 8257 is the DMA controller (d). So the code is (a), (b), (c), (d), option (A). The other options exchange the numbers, for example giving the 8051 to the USART or the 8257 to the interrupt controller, which is wrong.

Answer: B

The essential difference is that traps are synchronous and interrupts are asynchronous with the program. A trap is raised by the program itself, for example by an error such as division by zero or by a system call, and always happens at the same point when the program is run again. An interrupt comes from outside, for example from an I/O device, at an unpredictable moment.

Option A reverses the two, and option C ties interrupts to I/O devices only, which is not the defining contrast with the program.

Answer: B

An interrupt which arises from the illegal or erroneous use of an instruction or of data is an internal interrupt, also called a trap. Examples are an overflow, a division by zero, an invalid operation code or a violation of protection. The answer is (B).

A software interrupt is caused deliberately by an instruction such as a supervisor call, and an external interrupt comes from a device outside the processor such as an I/O unit or a timer. Option (D) is wrong since only the internal type arises in this way.