Memory Hierarchy Questions and Answers

Answer: A

Both statements are true. RAM is volatile memory, which loses its contents when power is switched off, and it has a limited storage capacity. Secondary memory is the storage other than RAM and ROM, such as hard disks, and it keeps data permanently. Marking either statement as false would be wrong, so the first option is correct. RAM is the main working memory of the computer, and secondary memory such as a hard disk or an SSD is where files are kept when the power is off.

Answer: C

The starting addresses are (0, 8, 16, 24).

Each block is selected by IA4 and IA3 through the decoder: IA4 IA3 = 00 enables X1, 01 enables X2, 10 enables X3 and 11 enables X4. The other ten lines (IA11 to IA5 and IA2 to IA0) form the address inside the block. The starting location of a block, Addr = 0, has all ten of those lines at 0, so only IA4 and IA3 can be 1:

\[ \begin{aligned} X1&: 0,\quad X2: 2^{3} = 8 \\ X3&: 2^{4} = 16,\quad X4: 2^{4} + 2^{3} = 24 \end{aligned} \]

(0, 1024, 2048, 3072) is what the usual design gives, with the two top lines IA11 and IA10 on the decoder; here the decoder sits on bits 4 and 3. (0, 1, 2, 3) would need IA1 and IA0 on the decoder. The four blocks cannot all start at address 0, because each address enables exactly one block.

Answer: D

All three are memory performance parameters, so the answer is (i), (ii) and (iii).

William Stallings gives three performance parameters for memory: access time (latency), the time to perform a read or write; memory cycle time, the access time plus any further time before a second access can start; and transfer rate, the rate at which data can be moved into or out of the memory unit.

Each option that leaves one of them out is therefore incomplete.

Answer: A

The key is (i) and (ii), access time and cycle time, and it rests on how the question reads the list.

Memory speed is set by two times: the access time \(t_{\mathrm{A}}\), from a request to the data being available, and the cycle time \(t_{c}\), the minimum gap between two successive operations. The access rate \(r_{\mathrm{A}}\) and the bandwidth \(r_{c}\) are the reciprocals of those two (\(r_{\mathrm{A}} = 1/t_{\mathrm{A}}\), \(r_{c} = 1/t_{c}\)), so they restate the same speed as rates rather than add a separate dependence.

On that reading A is the answer, and every option that adds (iii) or (iv) is wrong. A reader who counts the rates as parameters the speed depends on could choose D, and no source found settles which the question intends, so this follows the key.

Answer: C

Performance is enhanced by cache memory.

Cache is a small, very fast memory between the CPU and main memory. It holds copies of recently and frequently used instructions and data, so most memory accesses are served at cache speed, which cuts the average access time and keeps the CPU busy.

Auxiliary memory (disks) is far slower and used for bulk storage. Virtual memory enlarges the address space using disk, which adds overhead rather than speed. Associative memory is a technique for searching by content, used inside caches and TLBs, rather than the memory level that speeds up the CPU in general.

Answer: B

The memory used for temporary data during execution is RAM.

Random access memory is read-write and volatile, so programs keep their working data and variables there while they run, and it is lost when power is off.

ROM is read-only and holds fixed programs such as firmware. A hard disk is slow secondary storage for long-term data. Cache memory also holds temporary data, but it is a small, fast copy of part of RAM; the general working memory is RAM.

Answer: C

A secondary memory device is the Hard Disk.

Secondary memory is non-volatile, high-capacity storage that keeps data without power and is not directly addressed by the CPU: hard disks, SSDs, optical discs and pen drives.

RAM, cache memory and registers are primary or internal memory, used by the processor directly and losing their contents when power is off.

Answer: B

The maximum addressable memory is 4 GB.

A 32-bit address can take \(2^{32}\) distinct values, and with byte addressing each value names one byte:

\[ \begin{aligned} 2^{32}\ \text{bytes} &= 2^{2} \times 2^{30}\ \text{bytes} \\ &= 4\ \text{GB} \end{aligned} \]

2 GB is \(2^{31}\) bytes, the space a 31-bit address would reach. 8 GB and 16 GB would need 33 and 34 address bits.

Answer: D

The fastest memory of these is cache.

Cache memory is small, fast SRAM built into or right beside the processor. It holds copies of the data and instructions the processor is using most, so they can be read in a few clock cycles instead of waiting for main memory.

In the memory hierarchy, speed falls and size grows as you move away from the processor: registers, then cache, then main memory (RAM and ROM), then secondary storage such as a hard disk, which is thousands of times slower than RAM.

Answer: C

The address bus needs 15 lines.

Each address line doubles the number of locations that can be selected, so the width is the base-2 logarithm of the number of addressable bytes.

\[ \begin{aligned} 32\ \text{KB} &= 32 \times 1024 = 2^{5} \times 2^{10} \\ &= 2^{15}\ \text{bytes} \end{aligned} \]

So 15 address lines are needed for byte addressing. 10 lines address only 1 KB, 12 lines 4 KB, and 16 lines 64 KB, twice the memory given.