Interrupts and DMA Questions and Answers

Answer: B

RST 6 transfers execution to 0030 H.

The 8085 restart instruction RST n is a one-byte call to the address 8 × n. For n = 6 that is 48 in decimal, which is 30 in hexadecimal, so the vector is 0030H.

0024H is the vector of the TRAP interrupt (RST 4.5). 0048H writes the decimal value 48 as if it were hexadecimal, and 0060H would correspond to n = 12, which does not exist among RST 0 to RST 7.

Answer: C

SIM stands for set interrupt mask.

SIM takes the contents of the accumulator and uses them to mask or unmask the RST 7.5, 6.5 and 5.5 interrupts, reset the RST 7.5 flip-flop, and send a bit on the serial output data line SOD. Its companion RIM (read interrupt mask) reads the mask status, pending interrupts and the serial input SID.

'Select', 'sort' and 'subscribe' do not appear in the 8085 mnemonics; they are distractors built on the same initials.

Answer: D

The fastest I/O data transfer uses DMA.

In direct memory access, a DMA controller takes over the system bus and moves data directly between the I/O device and memory, without the processor fetching and executing an instruction for each byte. Transfers run at bus speed, which is why disks and other high-speed devices use DMA for block transfers.

Polled I/O wastes processor time testing device status, and interrupt-driven I/O still needs the processor to run a service routine for every transfer. Memory-mapped I/O is a way of addressing I/O ports, not a transfer method, and its transfers still pass through the processor.

Answer: C

These terms are used in direct memory access.

In DMA, a DMA controller must take over the system bus from the processor to transfer data directly between memory and a peripheral. It requests the bus (Bus Request, or HOLD in the 8085/8086), the processor grants it (Bus Grant, HLDA), and the logic that decides which master gets the bus is bus arbitration.

Serial communication, memory map design and address/data multiplexing involve no transfer of bus mastership, so these terms do not belong to them.

Answer: B

From lowest to highest priority the order is (1) (2) (3) (4): single step, INTR, NMI, divide error/INT n/INTO.

In the 8086 the internal (software and exception) interrupts such as divide error, INT n and INTO have the highest priority, followed by the non-maskable interrupt NMI, then the maskable hardware interrupt INTR. The single-step (trap) interrupt has the lowest priority.

Option A makes single step the highest priority, the reverse of the truth, and options C and D place NMI below INTR, so none matches the 8086 priority list.

Answer: C

In the 8051 the highest priority interrupt among those listed is IE0, external interrupt 0.

When interrupts of the same priority level are pending together, the 8051 resolves them by a fixed internal polling sequence:

1. IE0, external interrupt 0
2. TF0, timer 0 overflow
3. IE1, external interrupt 1
4. TF1, timer 1 overflow
5. RI/TI, serial port

So TF0 comes second, IE1 third and TF1 fourth. (Reset has the highest priority of all, but it is not one of the options.) The IP register can raise any source to the high priority level, but the question asks about the default order.

Answer: C

The 8085 interrupt priority, from highest, is TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR, so with the four given the order is TRAP, RST 7.5, RST 5.5, INTR, that is 2, 3, 4, 1 (option C).

Option A puts INTR first, but the INTR is the lowest of the hardware interrupts. Option B places INTR before RST 5.5, and D starts with RST 5.5, which is below TRAP and RST 7.5.

Answer: C

In the 8259 programmable interrupt controller, an interrupt request input that is left unconnected may pick up an accidental noise pulse and cause a false interrupt, so every unused interrupt line is connected to ground, which holds it permanently low and inactive. The key gives this action. Shorting the unused lines together would only join their noise, connecting them to Vcc would hold them at the active level for a level-sensitive input, and leaving them open is the situation the question wants to avoid, since an open input floats and picks up noise. The answer is that all unused interrupt lines are connected to ground.

Answer: C

From least to highest priority the sequence is IV, II, I, III, option (C). In the 8085, the maskable hardware interrupts rank as INTR, which is lowest, then RST 5.5, RST 6.5 and RST 7.5, and TRAP, which is the non-maskable one, has the highest priority. RST 0 is not one of the hardware interrupt pins; it is a restart instruction that is supplied through the INTR line, so it ranks lowest. So the order is RST 0, RST 5.5, RST 6.5, TRAP. Options (A) and (D) put TRAP at the bottom. Option (B) puts RST 6.5 below RST 5.5, which reverses their priority.