Counters Questions and Answers

Q: In a 4-bit binary counter, the maximum decimal number that can be represented is

The maximum is 15.A 4-bit counter has \(2^4 = 16\) states, from 0000 to 1111, that is 0 to 15. The largest number it can represent is \(2^4 - 1 = 15\).16 is the number of states, not the largest value, since counting starts at 0. 8 is the count for 3 bits and 31 the maximum for 5 bits.So a 4-bit counter is a mod-16 counter, counting 0 to 15 before returning to 0.

Q: Let k=2n. A circuit is built by giving the output of an n-bit binary counter as input to an n-to-2n bit decoder. This circuit is equivalent to a

The circuit is equivalent to a K-bit Ring counter.The n-bit binary counter steps through 0 to \(2^{n} - 1\). The decoder turns each count into exactly one active line out of \(k = 2^{n}\) outputs. As the count advances, the single 1 moves to the next output, and after the last one it returns to the first, just like the circulating 1 of a k-bit ring counter.A binary up or down counter would show the count as a binary number, and a Johnson counter fills with 1s and then 0s, so neither matches the one-hot output.

Q: Synchronous counters eliminate the delay problems encountered with asynchronous counters because the

The reason is that the input clock pulses are applied simultaneously to each stage.In an asynchronous (ripple) counter only the first flip-flop gets the clock; each later flip-flop is triggered by the output of the one before, so the propagation delays add up stage by stage and the count settles late. In a synchronous counter every flip-flop shares the same clock line and changes state at the same instant, so there is no accumulated delay.Clocking only the first and last stages, or only the last, would still leave stages waiting on one another, and a counter whose stages are not activated by the clock would not count at all.

21.

In a 4-bit binary counter, the maximum decimal number that can be represented is

A.8
B.15
C.16
D.31

Exam Year(s)

Tripura Public Service Commission - 2025,

Answer: B

The maximum is 15.

A 4-bit counter has \(2^4 = 16\) states, from 0000 to 1111, that is 0 to 15. The largest number it can represent is \(2^4 - 1 = 15\).

16 is the number of states, not the largest value, since counting starts at 0. 8 is the count for 3 bits and 31 the maximum for 5 bits.

So a 4-bit counter is a mod-16 counter, counting 0 to 15 before returning to 0.

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22.

Let k=2ⁿ. A circuit is built by giving the output of an n-bit binary counter as input to an n-to-2ⁿ bit decoder. This circuit is equivalent to a

A.K-bit binary up counter
B.K-bit binary down counter
C.K-bit Ring counter
D.K-bit Johnson counter

Exam Year(s)

Tripura Public Service Commission - 2025,

Answer: C

The circuit is equivalent to a K-bit Ring counter.

The n-bit binary counter steps through 0 to \(2^{n} - 1\). The decoder turns each count into exactly one active line out of \(k = 2^{n}\) outputs. As the count advances, the single 1 moves to the next output, and after the last one it returns to the first, just like the circulating 1 of a k-bit ring counter.

A binary up or down counter would show the count as a binary number, and a Johnson counter fills with 1s and then 0s, so neither matches the one-hot output.

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23.

Synchronous counters eliminate the delay problems encountered with asynchronous counters because the

A.input clock pulses are applied only to the first and last stages
B.input clock pulses are applied only to the last stage
C.input clock pulses are not used to activate any of the counter stages
D.input clock pulses are applied simultaneously to each stage

Exam Year(s)

Tripura Public Service Commission - 2019,

Answer: D

The reason is that the input clock pulses are applied simultaneously to each stage.

In an asynchronous (ripple) counter only the first flip-flop gets the clock; each later flip-flop is triggered by the output of the one before, so the propagation delays add up stage by stage and the count settles late. In a synchronous counter every flip-flop shares the same clock line and changes state at the same instant, so there is no accumulated delay.

Clocking only the first and last stages, or only the last, would still leave stages waiting on one another, and a counter whose stages are not activated by the clock would not count at all.

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24.

What are the final values of \(Q_1\) and \(Q_0\) after 4 clock cycles, if initial values are 00 in the sequential circuit shown below :

Two T flip-flops with T input held at 1; the clock Cx drives the first flip-flop, whose output Q0 clocks the second flip-flop, whose output is Q1

A.11
B.10
C.01
D.00

Exam Year(s)

UGC NET - 2012,

Answer: D

Both flip-flops are T flip-flops with T = 1, so each toggles whenever its clock input has an active edge. The first one is clocked by Cx, so \(Q_0\) toggles at every clock. The second one is clocked by \(Q_0\), so \(Q_1\) toggles when \(Q_0\) goes from 0 to 1. Starting from \(Q_1 Q_0 = 00\) the state after each clock is 11, 10, 01 and 00. After the fourth clock the circuit is back at 00, since it is a two bit ripple counter that counts down through 4 states. The keyed answer is 00.

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25.

The largest decimal number that can be stored in a MOD-64 counter is

A.64
B.15
C.16
D.63

Exam Year(s)

UGC NET - 2012,

Answer: D

A MOD-64 counter has 64 states, which run from 0 to 63, and it then returns to 0. So the largest decimal number it can store is 63, which is 111111 in binary for a six bit counter, since 2 to the power 6 is 64. The number 64 would need a seventh bit, so it cannot be held, and the values 15 and 16 are the figures for a MOD-16 counter, whose largest count is 15. The general rule is that the largest count of a MOD-N counter is N minus 1. The answer is 63.

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26.

How many Flip-Flops are required to build a binary counter circuit to count from 0 to 1023 ?

A.1
B.6
C.10
D.24

Exam Year(s)

UGC NET - 2012,

Answer: C

A binary counter that counts from 0 to 1023 has 1024 distinct states, and n flip-flops give 2ⁿ states, so we need \( 2^{n} \ge 1024 \), which gives n = 10 because \( 2^{10} = 1024 \). With 6 flip-flops the counter reaches only 64 states, with 1 flip-flop only 2, and 24 would be far more than needed (a counter of 24 flip-flops covers over 16 million states). The answer is option C.

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27.

What are the final values of Q₁ and Q₀ after 4 clock cycles, if initial values are 00 in the sequential circuit shown below :

Two T flip-flops. Both T inputs are tied to 1. The first flip-flop is clocked by Cx and its output Q0 is also the clock input of the second flip-flop, whose output is Q1.

A.11
B.10
C.01
D.00

Exam Year(s)

UGC NET - 2013,

Answer: D

The final values are Q1 Q0 = 00. Both T inputs are tied to 1, so each flip-flop toggles on its clock edge. The first flip-flop is clocked by Cx and the second by Q0, on a rising edge. Starting at 00: after clock 1, Q0 rises to 1 and Q1 toggles to 1, giving 11; after clock 2, Q0 falls to 0 with no edge for Q1, giving 10; after clock 3, Q0 rises and Q1 toggles to 0, giving 01; after clock 4, Q0 falls, giving 00.

The circuit is a 2-bit counter that returns to its start after 4 cycles.

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28.

A counter in which all the flip-flops receive the clock pulse at the same time is known as

A.ripple counter
B.synchronous counter
C.clocked counter
D.asynchronous counter

Exam Year(s)

UGC NET - 2013,

Answer: B

A synchronous counter has the same clock pulse applied to all its flip-flops at the same instant, so all the stages change state together and there is no cumulative propagation delay. In a ripple (asynchronous) counter each flip-flop is clocked by the output of the one before it, so the delays add up. 'Clocked counter' is not a standard type of counter. The answer is a synchronous counter.

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