Memory Devices Questions and Answers

Answer: B

Both statements are true but the reason does not explain the assertion, which is option (B). RAM is volatile, so its contents are lost as soon as power is removed. ROM is non-volatile and retains its contents. That ROM keeps its data says nothing about why RAM loses it, since RAM's volatility comes from storing bits in flip-flops or charged capacitors that need power. Option (A) wrongly links the two, and (C) and (D) deny a true statement.

Answer: C

The keyed answer is (A) true and (R) false. A programmable ROM can serve as a synchronous counter, because its output word can be fed back as the next address (through a register clocked together), and the stored contents then define the count sequence, so (A) is accepted. The reason is not accepted by the key: a PROM is programmed once, and the statement that each location can be read synchronously does not explain how it counts. The keyed option is C, and the options calling (A) false or (R) a valid explanation are wrong.

Answer: A

EEPROM (electrically erasable programmable read only memory) can be erased by an electrical signal, so it can be erased and rewritten in the circuit, while it is mounted on the motherboard. EPROM needs ultraviolet light through a quartz window, so it must be taken out of the board and put under a UV lamp. ROM is programmed at manufacture and cannot be erased, and PROM can be programmed once only by the user. The answer is EEPROM, option A.

Answer: D

The memory needs 15 address lines and 8 data lines.

A byte-organised memory stores one 8-bit byte at each address, so it needs 8 data lines. The number of address lines n must satisfy \(2^{n} = \) number of locations:

\[ \begin{aligned} 32\ \text{kB} &= 32 \times 1024 \\ &= 2^{5} \times 2^{10} = 2^{15} \end{aligned} \]

so 15 address lines are needed. 12 and 13 address lines would reach only 4 kB and 8 kB, and '32 and 1' confuses the capacity with the number of lines.

Answer: A

The answer is tACS : Chip select access time.

In memory timing, tACS is measured from the moment chip select (CS) goes active (low) to the moment valid data appears on the data bus. It is the minimum time the processor must wait after selecting the chip before it can read.

tAA (address access time) is measured from a stable address, not from CS. tLZ is the time from chip select until the outputs leave the high-impedance state (they are driven but not yet valid), and tHZ is the time for the outputs to return to tri-state after deselection.

Answer: A

The memory needed is 256 K bytes.

256 grey shades need 8 bits per pixel, since \(2^{8} = 256\), which is one byte per pixel.

\[ \begin{aligned} 512 \times 512 &= 262144 \text{ pixels} \\ &= 262144 \text{ bytes} \\ &= 256 \times 1024 = 256\ \text{K bytes} \end{aligned} \]

512 K bytes would mean 16 bits per pixel, 1 M byte 32 bits, and 64 K bytes only 2 bits per pixel (4 grey levels).

Answer: C

The correct code is (2) (4) (1) (3).

• (a) SRAM stores each bit in a flip-flop (a latch of cross-coupled transistors).
• (b) DRAM stores each bit as charge on a capacitor accessed through a MOSFET.
• (c) Flash memory stores charge on the floating gate of a floating-gate MOSFET.
• (d) A hard disk stores data magnetically.

Option B gives flash memory the magnetic storage of the hard disk, and options A and D misplace SRAM and DRAM.

Answer: A

The key's answer is Data bus is in series and address bus in parallel.

To widen the word, both chips must respond to the same address, so their address lines (and chip selects) are connected in common, in parallel. Their data lines are not shared: one chip supplies the lower bits and the other the upper bits, placed one after the other to form a bus twice as wide, which the paper calls the data bus in series. Two 1K × 4 chips connected this way make a 1K × 8 memory.

The opposite arrangement, data lines in common and the address range extended with a decoder, increases the number of words, not the word size. Connecting both buses in common would make the two chips drive the same data lines at once.

Answer: B

The minimum memory size is 10 bytes, as the key states.

A BCD to seven-segment decoder can be built as a look-up table in ROM. The input is a 4-bit BCD digit and the output is the seven segment lines a to g, which fit in one byte. Only the digits 0 to 9 are valid BCD, so ten locations of one byte each are enough: 10 bytes.

A physical ROM with four address lines has 16 locations, so a chip would be 16 bytes (option A); the six codes 1010 to 1111 are never used in BCD, which is why the minimum is 10. 8 bytes could hold only the digits 0 to 7, and 1 k byte is far larger than needed.

Answer: B

The write pulse width is the time for which \(\overline{\mathrm{WR}}\) goes low.

The write control line of a memory chip or peripheral is normally active low, which is why it is written with a bar. A write is performed while \(\overline{\mathrm{WR}}\) is held low, and the timing parameter \(t_{wp}\) is the minimum duration of that low pulse needed for the data to be written reliably.

\(\overline{\mathrm{WR}}\) high is its inactive state, and an active-high WR is not the signal the timing diagram describes, so the other options describe the idle condition or the wrong signal.