Logic Gates Questions and Answers

Answer: A

Both statements are correct and the reason explains the assertion, the first option. A NAND gate is called universal because any logic function can be realised with NAND gates alone, since NOT, AND and OR can each be built from NANDs.

The reason states exactly this property, so it is the explanation of the assertion. The options calling one of the statements false, or denying the explanation, are wrong.

Answer: B

The symbol has a curved back edge and a pointed front, and the output has no small circle (bubble) on it. That is the OR gate symbol: the output is high when either input is high. An AND gate has a flat back, a NAND gate is an AND with a bubble, and a NOT gate is a triangle with a bubble, drawn with one input. The answer is OR, option B.

Answer: D

The gate gives a high output only when exactly one of the two inputs is high, and a low output when both are low and also when both are high. That is the exclusive OR (XOR) gate, with the truth table 00 gives 0, 01 gives 1, 10 gives 1, 11 gives 0.

An ordinary OR gate gives a high output also when both inputs are high, so it does not fit the word 'only'. A NAND gate gives low only when both inputs are high, and a NOR gate gives high only when both are low. The answer is XOR, option D.

Answer: A

Trace the two branches of the diagram with \(A = 1\) and \(B = 0\). The top AND gate has the inputs A and B directly, so its output is \(A \cdot B = 1 \cdot 0 = 0\).

The bottom AND gate gets the inputs through the NOT gates, so its inputs are \(\bar{A} = 0\) and \(\bar{B} = 1\), and its output is \(0 \cdot 1 = 0\).

\[ Y = 0 + 0 = 0 \]

The OR gate gives 0 only when both of its inputs are 0, which is the case. Options 2 and 3 are not possible as the output of a logic gate, which is only 0 or 1, and 1 would need one of the AND outputs to be 1. The answer is 0, option A.

Answer: D

The correct option is P = 0, Q = 0; X = 1.

Both inputs of the NAND gate are tied to P, so it acts as an inverter and outputs \(\overline{P}\). The AND gate outputs \(PQ\). The OR gate combines them:

\[ X = \overline{P} + PQ = \overline{P} + Q \]

Check each option: with P = 0, Q = 0, \(X = 1 + 0 = 1\), as stated. With P = 1, Q = 1, \(X = 0 + 1 = 1\), not 0. With P = 1, Q = 0, \(X = 0 + 0 = 0\), not 1. With P = 0, Q = 1, \(X = 1\), not 0. So only the last option is consistent with the circuit.

Answer: A

The output is three pulses (A).

A NAND gate with both inputs tied together is an inverter, so the first two gates give P′ and Q′. The final NAND gives

\[ Y = (P' \cdot Q')' = P + Q \]

by De Morgan's law. So Y is high whenever P or Q is high. P has two pulses early on and Q one pulse later, at a time when P is low, so Y shows all three pulses.

Two pulses (B) would be P alone, ignoring Q. A flat zero (C) is P AND Q, which is never high since the pulses do not overlap. One long pulse (D) does not follow from any combination of these inputs.

Answer: A

The output is 1 only for \((P, Q) = (0, 0)\).

The upper branch gives \(\overline{P + Q}\) (OR followed by NOT, a NOR), and the lower branch gives \(\overline{Q}\). The AND gate combines them:

\[ \begin{aligned} T &= \overline{P + Q} \cdot \overline{Q} \\ &= \overline{P}\,\overline{Q} \cdot \overline{Q} = \overline{P}\,\overline{Q} \end{aligned} \]

So \(T = 1\) only when both inputs are 0. For (0,1), (1,1) and (1,0) at least one input is 1, the NOR output is 0, and the AND gate gives 0.

Answer: B

The NOR gate is faulty.

Check each gate against its own inputs. The first NOT gate is fine: pin 2 (1, 0, 1, 0, 1, 0) is the inverse of pin 1 (0, 1, 0, 1, 0, 1). The output NOT gate is fine: pin 5 (1, 1, 0, 1, 1, 1) is the inverse of pin 4 (0, 0, 1, 0, 0, 0).

A working NOR gate gives 1 only when both inputs are 0. With pin 2 = 1, 0, 1, 0, 1, 0 and pin 3 = 0, 0, 1, 1, 0, 0, both are 0 in intervals 2 and 6, so pin 4 should read 0, 1, 0, 0, 0, 1. It actually reads 0, 0, 1, 0, 0, 0, high only when both inputs are 1, which is AND behaviour. So the NOR gate alone is at fault, and the options blaming either NOT gate, or both the NOR and the output NOT gate, are ruled out by the checks above.

Answer: C

The circuit performs the OR operation.

The NOR gate gives \(\overline{A + B}\). A NAND gate with both inputs tied together acts as an inverter, since \(\overline{X \cdot X} = \overline{X}\). So

\[ Y = \overline{\overline{A + B}} = A + B \]

which is OR. NOR would be the output of the first gate alone, without the inverting NAND. AND and NAND would need the inputs to be combined by an AND-type gate first, but here they enter a NOR gate.

Answer: D

The staircase switch is represented by XOR (Exclusive-OR).

A staircase (two-way) light can be switched on or off from either end. Flipping either switch alone changes the state of the lamp, which is exactly the behaviour of XOR: the output changes whenever exactly one input changes. Taking both switches in the same position as 'off', the lamp is on when the two switch positions differ:

\[ L = A \oplus B \]

OR and NOR do not toggle on every change (with OR, once one switch is on, flipping the other does nothing). XNOR also toggles, but it describes the same circuit with the opposite labelling of the rest position, and the conventional textbook answer for the staircase circuit is XOR.