Match List-I with List-II :List I : RegisterList II : Use(a) IP(i) Loop operations(b) CX(ii) String manipulation(c) SI(iii) Modular programming(d) SP(iv) Code access

The correct matching is a-iv, b-i, c-ii, d-iii.(a) IP, the instruction pointer, holds the offset of the next instruction in the code segment: code access (iv).(b) CX is the count register used by LOOP and REP: loop operations (i).(c) SI, the source index, points to the source in string instructions such as MOVS: string manipulation (ii).(d) SP, the stack pointer, manages the stack used by CALL and RET to run subroutines, the basis of modular programming (iii).The other codes swap the loop counter and the string index or misplace IP.

8086 Architecture and Addressing Modes Questions and Answers

Q: The width of the instruction queue/pipeline in 8086 microprocessor is :

The 8086 instruction queue is 6 bytes long.The bus interface unit of the 8086 prefetches instruction bytes into a 6-byte first-in, first-out queue while the execution unit is busy decoding and executing earlier instructions. This overlap of fetch and execute is a simple form of pipelining and speeds up execution.The 8088, which has an 8-bit external data bus, has a 4-byte queue, which is the usual source of the 4-byte distractor. 8 bytes and 2 bytes are not the queue length of either processor.

Q: 8086 works in multiprocessing mode with the help of :

The 8086 works in multiprocessing mode with the help of max mode.The 8086 has two modes, selected by the MN/MX pin. In minimum mode (pin high) it generates all bus control signals itself and is used as the only processor. In maximum mode (pin low) the bus control signals are produced by the 8288 bus controller, and pins such as RQ/GT and LOCK let the 8086 share the system bus with coprocessors like the 8087 and other processors, a multiprocessor configuration.Minimum mode is for single-processor systems. Virtual memory is not a feature of the 8086, and DMA is a data transfer method, not a processor mode.

Q: If the contents of code segment register of 8086 is 1000H and the instruction pointer is loaded with 0134H, then the instruction will be fetched from :

The instruction is fetched from 10134H.The 8086 forms a 20-bit physical address by shifting the segment register left by one hex digit (multiplying by 16) and adding the offset:\[ \begin{aligned} PA &= CS \times 10H + IP \\ &= 10000H + 0134H \\ &= 10134H \end{aligned} \]10000H is only the segment base, 0134H is only the offset, and 1134H adds the two without shifting the segment value.

Q: The correct sequence of execution of Read/Write instruction in 8086 Min mode of operation is :

The sequence is set MN/MX high, output high on M/IO, set ALE, transfer data.Minimum mode is selected by tying MN/MX high. In a bus cycle, the 8086 first drives M/IO to show whether a memory or I/O location is addressed (high for memory), puts the address on the multiplexed bus and pulses ALE so that the address is latched, and only then, with the address held in the latches, transfers data on the same lines with RD or WR.The other options transfer data before the address is latched, set ALE last, or use MN/MX low, which selects maximum mode.

Q: The maximum and the minimum size of a segment in 8086 is :

The maximum and minimum segment sizes in the 8086 are 64 K and 16 bytes.An 8086 offset is a 16-bit number, so a segment can span at most 216 = 65536 bytes, 64 K. A segment must start at an address that is a multiple of 16 (a paragraph boundary), because the 20-bit physical address is the segment register shifted left by four bits plus the offset. Consecutive segment starts are therefore 16 bytes apart, and the smallest segment that does not overlap the next is 16 bytes.32 K and 16 K understate the 16-bit offset range, and 256 bytes is not the paragraph size.

Q: Advantage of segmented addressing is :

The keyed advantage is that the size of a segment is variable.Segmentation divides memory into logical blocks such as code, data and stack, each defined by a base address and a length. Unlike pages, which all have one fixed size, a segment can be made as large as the module it holds (in the 8086, any size up to 64 KB, since segments may overlap), which suits programs whose parts have different sizes and makes programs relocatable.A fixed size is a property of paging, not segmentation. Pipelining and DMA are unrelated to how addresses are formed.

Q: The effective address, if segment register is 3000 and offset is 2020 will be :

The physical address is 32020 (hexadecimal).In the 8086 the 20-bit physical address is the segment value shifted left by four bits (multiplied by 10H) plus the 16-bit offset:\[ \begin{aligned} 3000\text{H} \times 10\text{H} &= 30000\text{H} \\ 30000\text{H} + 2020\text{H} &= 32020\text{H} \end{aligned} \]30002 comes from writing the offset digits wrongly, 05020 from adding without the shift, and 23020 from shifting the offset instead of the segment.

Q: Pipelining is implemented in 8086 with :

Pipelining in the 8086 uses the queue register in the BIU, which is FIFO.The 8086 is divided into a bus interface unit (BIU) and an execution unit (EU). While the EU executes one instruction, the BIU fetches the following instruction bytes from memory and stores them in a 6-byte instruction queue. The bytes are taken out in the order they were fetched, first in first out, so fetching and execution overlap.A LIFO queue would hand the EU the most recently fetched byte first, which would scramble the program. Segmented addressing and direct memory access are features of how memory is addressed and accessed, not the mechanism of pipelining.

Q: In 8086 which of the following is not true ?

The statement that is not true is co-processor is interfaced in minimum mode.The 8086 can work in minimum mode, as a single processor that generates its own bus control signals, or in maximum mode, for multiprocessor systems in which the 8288 bus controller generates them. The 8087 numeric co-processor needs the queue status and request/grant lines available only in maximum mode, so it is interfaced in maximum mode.The other statements are true: the 8086 uses pipelining through its instruction queue, it uses segmented addressing with CS, DS, SS and ES, and it consists of an execution unit and a bus interface unit.

The width of the instruction queue/pipeline in 8086 microprocessor is :

A.4-bytes
B.6-bytes
C.8-bytes
D.2-bytes

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: B

The 8086 instruction queue is 6 bytes long.

The bus interface unit of the 8086 prefetches instruction bytes into a 6-byte first-in, first-out queue while the execution unit is busy decoding and executing earlier instructions. This overlap of fetch and execute is a simple form of pipelining and speeds up execution.

The 8088, which has an 8-bit external data bus, has a 4-byte queue, which is the usual source of the 4-byte distractor. 8 bytes and 2 bytes are not the queue length of either processor.

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8086 works in multiprocessing mode with the help of :

A.Virtual memory
B.DMA mode
C.Max mode
D.Minimum mode

Exam Year(s)

MH SET - 2019, SET Exam - 2019,

Answer: C

The 8086 works in multiprocessing mode with the help of max mode.

The 8086 has two modes, selected by the MN/MX pin. In minimum mode (pin high) it generates all bus control signals itself and is used as the only processor. In maximum mode (pin low) the bus control signals are produced by the 8288 bus controller, and pins such as RQ/GT and LOCK let the 8086 share the system bus with coprocessors like the 8087 and other processors, a multiprocessor configuration.

Minimum mode is for single-processor systems. Virtual memory is not a feature of the 8086, and DMA is a data transfer method, not a processor mode.

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If the contents of code segment register of 8086 is 1000H and the instruction pointer is loaded with 0134H, then the instruction will be fetched from :

A.10000H
B.0134H
C.10134H
D.1134H

Exam Year(s)

MH SET - 2019, SET Exam - 2019,

Answer: C

The instruction is fetched from 10134H.

The 8086 forms a 20-bit physical address by shifting the segment register left by one hex digit (multiplying by 16) and adding the offset:

\[ \begin{aligned} PA &= CS \times 10H + IP \\ &= 10000H + 0134H \\ &= 10134H \end{aligned} \]

10000H is only the segment base, 0134H is only the offset, and 1134H adds the two without shifting the segment value.

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The correct sequence of execution of Read/Write instruction in 8086 Min mode of operation is :

A.Set \(MN/\overline{MX}\) high, Output high on \(M/\overline{IO}\), Set ALE, Transfer data
B.Set \(MN/\overline{MX}\) low, Output high on \(M/\overline{IO}\), Transfer data, Set ALE
C.Output high on \(M/\overline{IO}\), Transfer data, Set ALE, Set \(MN/\overline{MX}\) high
D.Transfer data, Set ALE, Set \(MN/\overline{MX}\) high, Output high on \(M/\overline{IO}\)

Exam Year(s)

MH SET - 2019, SET Exam - 2019,

Answer: A

The sequence is set MN/MX high, output high on M/IO, set ALE, transfer data.

Minimum mode is selected by tying MN/MX high. In a bus cycle, the 8086 first drives M/IO to show whether a memory or I/O location is addressed (high for memory), puts the address on the multiplexed bus and pulses ALE so that the address is latched, and only then, with the address held in the latches, transfers data on the same lines with RD or WR.

The other options transfer data before the address is latched, set ALE last, or use MN/MX low, which selects maximum mode.

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Match List-I with List-II :

List I : Register	List II : Use
(a) IP	(i) Loop operations
(b) CX	(ii) String manipulation
(c) SI	(iii) Modular programming
(d) SP	(iv) Code access

A.a-iv, b-ii, c-iii, d-i
B.a-ii, b-i, c-iii, d-iv
C.a-iv, b-i, c-ii, d-iii
D.a-i, b-iii, c-ii, d-iv

Exam Year(s)

MH SET - 2019, SET Exam - 2019,

Answer: C

The correct matching is a-iv, b-i, c-ii, d-iii.

(a) IP, the instruction pointer, holds the offset of the next instruction in the code segment: code access (iv).
(b) CX is the count register used by LOOP and REP: loop operations (i).
(c) SI, the source index, points to the source in string instructions such as MOVS: string manipulation (ii).
(d) SP, the stack pointer, manages the stack used by CALL and RET to run subroutines, the basis of modular programming (iii).

The other codes swap the loop counter and the string index or misplace IP.

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The maximum and the minimum size of a segment in 8086 is :

A.64 K, 16 bytes
B.32 K, 256 bytes
C.16 K, 16 bytes
D.64 K, 256 bytes

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: A

The maximum and minimum segment sizes in the 8086 are 64 K and 16 bytes.

An 8086 offset is a 16-bit number, so a segment can span at most 2¹⁶ = 65536 bytes, 64 K. A segment must start at an address that is a multiple of 16 (a paragraph boundary), because the 20-bit physical address is the segment register shifted left by four bits plus the offset. Consecutive segment starts are therefore 16 bytes apart, and the smallest segment that does not overlap the next is 16 bytes.

32 K and 16 K understate the 16-bit offset range, and 256 bytes is not the paragraph size.

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Advantage of segmented addressing is :

A.Size of segment is fixed
B.Size of segment is variable
C.Used in pipelining
D.Supports DMA

Exam Year(s)

MH SET - 2021, SET Exam - 2021,

Answer: B

The keyed advantage is that the size of a segment is variable.

Segmentation divides memory into logical blocks such as code, data and stack, each defined by a base address and a length. Unlike pages, which all have one fixed size, a segment can be made as large as the module it holds (in the 8086, any size up to 64 KB, since segments may overlap), which suits programs whose parts have different sizes and makes programs relocatable.

A fixed size is a property of paging, not segmentation. Pipelining and DMA are unrelated to how addresses are formed.

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The effective address, if segment register is 3000 and offset is 2020 will be :

A.30002
B.32020
C.05020
D.23020

Exam Year(s)

MH SET - 2021, SET Exam - 2021,

Answer: B

The physical address is 32020 (hexadecimal).

In the 8086 the 20-bit physical address is the segment value shifted left by four bits (multiplied by 10H) plus the 16-bit offset:

\[ \begin{aligned} 3000\text{H} \times 10\text{H} &= 30000\text{H} \\ 30000\text{H} + 2020\text{H} &= 32020\text{H} \end{aligned} \]

30002 comes from writing the offset digits wrongly, 05020 from adding without the shift, and 23020 from shifting the offset instead of the segment.

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Pipelining is implemented in 8086 with :

A.Segmented addressing
B.Queue register in BIU which is LIFO
C.Queue register in BIU which is FIFO
D.Direct memory access

Exam Year(s)

MH SET - 2023, SET Exam - 2023,

Answer: C

Pipelining in the 8086 uses the queue register in the BIU, which is FIFO.

The 8086 is divided into a bus interface unit (BIU) and an execution unit (EU). While the EU executes one instruction, the BIU fetches the following instruction bytes from memory and stores them in a 6-byte instruction queue. The bytes are taken out in the order they were fetched, first in first out, so fetching and execution overlap.

A LIFO queue would hand the EU the most recently fetched byte first, which would scramble the program. Segmented addressing and direct memory access are features of how memory is addressed and accessed, not the mechanism of pipelining.

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10.

In 8086 which of the following is not true ?

A.Pipelining is implemented
B.Segmented addressing is used
C.Co-processor is interfaced in minimum mode
D.Consists of Execution unit and Bus interface unit

Exam Year(s)

MH SET - 2023, SET Exam - 2023,

Answer: C

The statement that is not true is co-processor is interfaced in minimum mode.

The 8086 can work in minimum mode, as a single processor that generates its own bus control signals, or in maximum mode, for multiprocessor systems in which the 8288 bus controller generates them. The 8087 numeric co-processor needs the queue status and request/grant lines available only in maximum mode, so it is interfaced in maximum mode.

The other statements are true: the 8086 uses pipelining through its instruction queue, it uses segmented addressing with CS, DS, SS and ES, and it consists of an execution unit and a bus interface unit.

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