Timers and Counters Questions and Answers

Q: Assertion (A) : PWM signal can be easily generated by 8051.Reason (R) : It has built in timer/count.

The answer is both (A) and (R) are true and (R) is the correct explanation of (A).A PWM signal needs a fixed period and an adjustable on-time. The 8051's built-in timer/counters can time both intervals: a timer interrupt toggles a port pin and reloads the timer with the on-time or the off-time in turn, so the duty cycle is set in software without busy-waiting.The timers are what make PWM easy on the 8051, so R explains A. (The basic 8051 has no dedicated PWM module; derivatives with a PCA add hardware PWM, but the timer method works on every 8051.)

Q: The timer 0 of 8051 with 1 MHz clock can generate maximum delay of .................. with resolution ................ .

The maximum delay is about 64 ms, with a resolution of 1 μs.Taking the 1 MHz clock as the rate at which timer 0 counts, each count lasts 1 μs, which is the resolution. In mode 1, timer 0 is a 16-bit counter, so the longest delay before overflow is:\[ \begin{aligned} 2^{16} \times 1\ \mu\text{s} &= 65536\ \mu\text{s} \\ &\approx 65.5\ \text{ms} \approx 64\ \text{ms} \end{aligned} \]The key rounds 65.536 ms to 64 ms (64 K counts). 256 ms would need a 4 μs count, and 64 μs with 1 ms or 32 μs with 100 ms put the delay below the resolution, which is impossible.

Q: What is the frequency of the clock that is being used as the clock source for the timer ?

When used as a timer, the clock source is the controller's crystal frequency/12.In the 8051, a timer/counter set as a timer (C/T bit = 0 in TMOD) counts machine cycles. One machine cycle of the standard 8051 is 12 oscillator periods, so the timer register is incremented at \(f/12\). With an 11.0592 MHz crystal, for example, the timer ticks at 921.6 kHz.When the same block is set as a counter (C/T = 1) it counts pulses applied externally on the T0 or T1 pin instead. Those pulses are not divided by 12, and the crystal frequency itself is never applied to the timer undivided.

Q: What steps are followed when we need to turn on any timer ?

The steps are: load the TMOD register, load the count, start the timer, keep monitoring it, stop the timer.On the 8051, a timer is used as follows:Load TMOD to select the timer, its mode (for example 16-bit mode 1) and whether it counts as a timer or counter.Load the initial count into TH and TL.Start the timer by setting TR0 or TR1 in TCON.Monitor the overflow flag TF0 or TF1 (or use the interrupt).Stop the timer by clearing TR, and clear the TF flag.Leaving out TMOD leaves the mode undefined. Starting the timer before loading the count makes it count from the wrong value. 'Divide TCON by 2' is not an operation; TCON holds control bits, not a count.

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Assertion-Reason type questions : The following items consist of two statements, one labelled as 'Assertion (A)', and the other labelled the 'Reason (R)'. You are to examine these two statements and decide if the Assertion (A) and the Reason (R) are individually true and if so, whether the reason is a correct explanation of the Assertion. Select your answer to these items using the codes given below and mark your answer sheet accordingly.

Codes :
(A) Both (A) and (R) are true and (R) is the correct explanation of (A)
(B) Both (A) and (R) are true but (R) is not the correct explanation of (A)
(C) (A) is true but (R) is false
(D) (A) is false and (R) is true

Assertion (A) : PWM signal can be easily generated by 8051.

Reason (R) : It has built in timer/count.

A.Both (A) and (R) are true and (R) is the correct explanation of (A)
B.Both (A) and (R) are true but (R) is not the correct explanation of (A)
C.(A) is true but (R) is false
D.(A) is false and (R) is true

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: A

The answer is both (A) and (R) are true and (R) is the correct explanation of (A).

A PWM signal needs a fixed period and an adjustable on-time. The 8051's built-in timer/counters can time both intervals: a timer interrupt toggles a port pin and reloads the timer with the on-time or the off-time in turn, so the duty cycle is set in software without busy-waiting.

The timers are what make PWM easy on the 8051, so R explains A. (The basic 8051 has no dedicated PWM module; derivatives with a PCA add hardware PWM, but the timer method works on every 8051.)

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The timer 0 of 8051 with 1 MHz clock can generate maximum delay of .................. with resolution ................ .

A.64 ms, 1 μs
B.64 μs, 1 ms
C.32 μs, 100 ms
D.256 ms, 1 μs

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: A

The maximum delay is about 64 ms, with a resolution of 1 μs.

Taking the 1 MHz clock as the rate at which timer 0 counts, each count lasts 1 μs, which is the resolution. In mode 1, timer 0 is a 16-bit counter, so the longest delay before overflow is:

\[ \begin{aligned} 2^{16} \times 1\ \mu\text{s} &= 65536\ \mu\text{s} \\ &\approx 65.5\ \text{ms} \approx 64\ \text{ms} \end{aligned} \]

The key rounds 65.536 ms to 64 ms (64 K counts). 256 ms would need a 4 μs count, and 64 μs with 1 ms or 32 μs with 100 ms put the delay below the resolution, which is impossible.

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What is the frequency of the clock that is being used as the clock source for the timer ?

A.some externally applied frequency f'
B.controller's crystal frequency f
C.controller's crystal frequency/12
D.externally applied frequency/12

Exam Year(s)

MH SET - 2024, SET Exam - 2024,

Answer: C

When used as a timer, the clock source is the controller's crystal frequency/12.

In the 8051, a timer/counter set as a timer (C/T bit = 0 in TMOD) counts machine cycles. One machine cycle of the standard 8051 is 12 oscillator periods, so the timer register is incremented at \(f/12\). With an 11.0592 MHz crystal, for example, the timer ticks at 921.6 kHz.

When the same block is set as a counter (C/T = 1) it counts pulses applied externally on the T0 or T1 pin instead. Those pulses are not divided by 12, and the crystal frequency itself is never applied to the timer undivided.

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What steps are followed when we need to turn on any timer ?

A.load the count, start the timer, keep monitoring it, stop the timer
B.load the TMOD register, load the count, start the timer, keep monitoring it, stop the timer
C.load the TMOD register, start the timer, load the count, keep monitoring it, stop the timer
D.load the count, divide TCON by 2, start the timer, keep monitoring it, stop the timer

Exam Year(s)

MH SET - 2025, SET Exam - 2025,

Answer: B

The steps are: load the TMOD register, load the count, start the timer, keep monitoring it, stop the timer.

On the 8051, a timer is used as follows:

Load TMOD to select the timer, its mode (for example 16-bit mode 1) and whether it counts as a timer or counter.
Load the initial count into TH and TL.
Start the timer by setting TR0 or TR1 in TCON.
Monitor the overflow flag TF0 or TF1 (or use the interrupt).
Stop the timer by clearing TR, and clear the TF flag.

Leaving out TMOD leaves the mode undefined. Starting the timer before loading the count makes it count from the wrong value. 'Divide TCON by 2' is not an operation; TCON holds control bits, not a count.

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For using 8253 in counter mode from a initial value.

I. The control world for selection of counter is done.
II. The initial value will be kept in the counter before the selection of counter.
III. Selection of BCD mode is done.
IV. The initial value will be loaded to counter after the selection of counter.

A.I, III and IV are to be fulfilled.
B.I, II and III are to be fulfilled.
C.II, III and IV are to be fulfilled.
D.II, I and IV are to be fulfilled.

Exam Year(s)

UGC NET - 2012,

Answer: A

To use the 8253 timer in counter mode from an initial value, the programmer first writes a control word, which selects the counter, sets the operating mode and chooses binary or BCD counting, and only after that loads the initial count into the selected counter. So statements I, III and IV are the required steps: I, the control word for selecting the counter, III, the selection of BCD or binary mode, which is part of that word, and IV, loading the initial value after the counter is selected. Statement II is wrong, because the count cannot be loaded before the counter has been selected by the control word. The answer is that I, III and IV are to be fulfilled.

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In 8253 programmable interval timer, in which modes, the counting is neither enabled nor disabled ?

A.0 and 4
B.1 and 5
C.1 and 4
D.3 and 5

Exam Year(s)

UGC NET - 2013,

Answer: B

The counting is neither enabled nor disabled by the gate in modes 1 and 5, the second option. These are the hardware-triggered one-shot and strobe modes of the 8253, in which the rising edge of the gate triggers the count and later changes in the gate level do not stop it.

The other options include modes 0, 3 and 4, in which the gate level does enable or disable counting, so they are wrong.

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Timers and Counters Questions and Answers

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