8051 Microcontroller Architecture Questions and Answers

Q: An internal RAM memory of the 8051 is :

The internal RAM of the 8051 is 128 bytes.The 8051 microcontroller has 128 bytes of on-chip data RAM (addresses 00H to 7FH), holding four register banks of 8 registers each, a 16-byte bit-addressable area and a general-purpose scratch pad. It also has 4 KB of on-chip ROM and can address 64 KB of external memory.32 bytes is only the four register banks, 64 bytes is not an 8051 figure, and 64 KB is the external program or data memory space, not internal RAM. The 8052 variant doubles the internal RAM to 256 bytes.

Q: Microcontroller 8051 operates with 12 MHz oscillator and one machine cycle is defined as 12 oscillator periods. The execution time for a 4 machine cycle instruction would therefore be :

The execution time is 4 µs.\[ \begin{aligned} T_{osc} &= \frac{1}{12\ \text{MHz}} = \frac{1}{12}\ \mu s \\ T_{cycle} &= 12 \times \frac{1}{12}\ \mu s = 1\ \mu s \\ T_{instr} &= 4 \times 1\ \mu s = 4\ \mu s \end{aligned} \]With the usual 12 MHz crystal, each machine cycle of the 8051 takes exactly 1 µs, so a 4-cycle instruction (such as MUL or DIV) takes 4 µs. 1 µs is a single machine cycle, and 8 µs or 2 µs would need a 6 MHz or 24 MHz clock.

Q: Which of the following special function registers of 8051 is not bit addressible ?

The SFR that is not bit addressable is SBUF, the serial data buffer.In the 8051, only the special function registers whose addresses end in 0H or 8H (divisible by 8) are bit addressable. ACC is at E0H, PSW at D0H and port P0 at 80H, so their individual bits can be set, cleared and tested with bit instructions.SBUF is at 99H, which does not end in 0 or 8, so it can only be read or written as a whole byte.

Q: Vector addresses of 8051 interrupts are located in :

The 8051 interrupt vectors are located in 0000-0023H.The interrupt vectors are fixed addresses at the bottom of program memory (ROM). Reset starts execution at 0000H, and the five interrupts vector to 0003H (external INT0), 000BH (timer 0), 0013H (external INT1), 001BH (timer 1) and 0023H (serial port), each with 8 bytes of space.They are in code memory, not in on-chip RAM, and with an internal ROM they are not in external memory; 0001-1000H does not correspond to the vector table.

Q: 8051 has 8 bit data bus, but it can generate 16 bit addresses using :

The 8051 generates 16-bit addresses with the help of ALE.Port 0 of the 8051 is multiplexed: it first carries the low byte of the address (A0-A7) and then the data byte. The Address Latch Enable (ALE) pulse tells an external latch (such as a 74LS373) to capture the low address byte, while port 2 supplies the high byte (A8-A15). Together they form the 16-bit address even though the data bus is only 8 bits.IO/M is an 8085 signal, and R/W is a generic read-write line, neither of which latches addresses. The EA pin selects whether the 8051 executes from internal or external program memory.

Q: The alternate function of 8051 port 2 is :

The alternate function of port 2 is sending the higher order address (A8-A15).When the 8051 accesses external memory, port 2 outputs the upper byte of the 16-bit address, while port 0 carries the lower byte multiplexed with data.The data byte D0-D7 and the lower address A0-A7 are the alternate functions of port 0. Serial input and output (RXD, TXD) are alternate functions of port 3.

Q: On power up, the 8051 uses following locations in the RAM for registers Ro - RI and bit addressable memory :

The locations are 00 - 07 and 20 - 2F.On reset the 8051 selects register bank 0, so R0-R7 (printed Ro - RI) occupy internal RAM addresses 00H to 07H. Banks 1 to 3 follow up to 1FH. The bit-addressable area is the 16 bytes from 20H to 2FH, giving 128 individually addressable bits, and the general-purpose scratch area runs from 30H to 7FH.00-7F is the whole lower internal RAM and 80-FF holds the special function registers. 30-7F is the scratch area, not the register bank.

Q: After reset, SP register in 8051 is initialized to address .............. .

After reset, SP is initialised to 07H.On reset, the 8051 loads the stack pointer with 07H. Because the 8051 increments SP before it stores data, the first byte pushed goes to location 08H, the start of register bank 1. Programs that use banks 1 to 3 usually move the stack higher.08H is where the first pushed byte lands, not the reset value of SP. 09H and 06H have no special role at reset.

Q: What is the address range of SFR Register bank ?

The SFR address range is 80H - FFH.In the 8051 the special function registers, such as the accumulator, B, PSW, SP, DPTR, the port latches and the timer and serial registers, occupy the upper 128 bytes of the direct address space, 80H to FFH. Only some of these addresses are actually used.00H to 7FH is the internal RAM (register banks, bit-addressable area and scratch pad), so 00H - 77H is part of RAM. 40H - 80H straddles RAM and the SFRs, and 80H - 7FH is not a valid range.

Direction for [ Question No: 1 To 1 ] :

Directions : The following items consist of two statements, one labelled the "Assertion (A)" and the other labelled the "Reason (R)". You are to examine these two statements carefully and decide if the Assertion (A) and the Reason (R) are individually true and if so, whether the Reason is a correct explanation of the Assertion. Select your answers to these items using the codes given below and mark your answer accordingly.

Assertion (A) : Microcontrollers are preferred in Real time applications.

Reason (R) : The on chip I/O integration has no bearing on the speed of microcontroller.

A.Both (A) and (R) are true and (R) is the correct explanation of (A).
B.Both (A) and (R) are true, but (R) is not correct explanation of (A).
C.(A) is true, but (R) is false.
D.(A) is false, but (R) is true.

Exam Year(s)

UGC NET - 2012,

Answer: C

The assertion is true and the reason is false (option C). Microcontrollers are preferred in real-time applications because the processor, memory, timers, interrupts and I/O are on one chip and so respond quickly and predictably.

The reason says that the on-chip I/O integration has no bearing on speed, which is wrong: the integration is what removes slow external buses and gives short response times. Options A and B accept the reason, and D rejects the assertion.

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An internal RAM memory of the 8051 is :

A.32 bytes
B.64 bytes
C.128 bytes
D.64 k bytes

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: C

The internal RAM of the 8051 is 128 bytes.

The 8051 microcontroller has 128 bytes of on-chip data RAM (addresses 00H to 7FH), holding four register banks of 8 registers each, a 16-byte bit-addressable area and a general-purpose scratch pad. It also has 4 KB of on-chip ROM and can address 64 KB of external memory.

32 bytes is only the four register banks, 64 bytes is not an 8051 figure, and 64 KB is the external program or data memory space, not internal RAM. The 8052 variant doubles the internal RAM to 256 bytes.

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Microcontroller 8051 operates with 12 MHz oscillator and one machine cycle is defined as 12 oscillator periods. The execution time for a 4 machine cycle instruction would therefore be :

A.4 µs
B.8 µs
C.1 µs
D.2 µs

Exam Year(s)

MH SET - 2019, SET Exam - 2019,

Answer: A

The execution time is 4 µs.

\[ \begin{aligned} T_{osc} &= \frac{1}{12\ \text{MHz}} = \frac{1}{12}\ \mu s \\ T_{cycle} &= 12 \times \frac{1}{12}\ \mu s = 1\ \mu s \\ T_{instr} &= 4 \times 1\ \mu s = 4\ \mu s \end{aligned} \]

With the usual 12 MHz crystal, each machine cycle of the 8051 takes exactly 1 µs, so a 4-cycle instruction (such as MUL or DIV) takes 4 µs. 1 µs is a single machine cycle, and 8 µs or 2 µs would need a 6 MHz or 24 MHz clock.

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Which of the following special function registers of 8051 is not bit addressible ?

A.Accumulator (ACC)
B.Program Status Word (PSW)
C.Port O (PO)
D.Serial Data Buffer (SBUF)

Exam Year(s)

MH SET - 2019, SET Exam - 2019,

Answer: D

The SFR that is not bit addressable is SBUF, the serial data buffer.

In the 8051, only the special function registers whose addresses end in 0H or 8H (divisible by 8) are bit addressable. ACC is at E0H, PSW at D0H and port P0 at 80H, so their individual bits can be set, cleared and tested with bit instructions.

SBUF is at 99H, which does not end in 0 or 8, so it can only be read or written as a whole byte.

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Vector addresses of 8051 interrupts are located in :

A.On-chip RAM
B.0000-0023H
C.0001-1000H
D.External memory

Exam Year(s)

MH SET - 2019, SET Exam - 2019,

Answer: B

The 8051 interrupt vectors are located in 0000-0023H.

The interrupt vectors are fixed addresses at the bottom of program memory (ROM). Reset starts execution at 0000H, and the five interrupts vector to 0003H (external INT0), 000BH (timer 0), 0013H (external INT1), 001BH (timer 1) and 0023H (serial port), each with 8 bytes of space.

They are in code memory, not in on-chip RAM, and with an internal ROM they are not in external memory; 0001-1000H does not correspond to the vector table.

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8051 has 8 bit data bus, but it can generate 16 bit addresses using :

A.\(IO/\overline{M}\)
B.ALE
C.\(R/\overline{W}\)
D.\(\overline{EA}\)

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: B

The 8051 generates 16-bit addresses with the help of ALE.

Port 0 of the 8051 is multiplexed: it first carries the low byte of the address (A0-A7) and then the data byte. The Address Latch Enable (ALE) pulse tells an external latch (such as a 74LS373) to capture the low address byte, while port 2 supplies the high byte (A8-A15). Together they form the 16-bit address even though the data bus is only 8 bits.

IO/M is an 8085 signal, and R/W is a generic read-write line, neither of which latches addresses. The EA pin selects whether the 8051 executes from internal or external program memory.

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The alternate function of 8051 port 2 is :

A.Input/output data \((D_{0} - D_{7})\)
B.Sending higher order address \((A_{8} - A_{15})\)
C.Sending lower order address \((A_{0} - A_{7})\)
D.Serial input/output

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: B

The alternate function of port 2 is sending the higher order address (A₈-A₁₅).

When the 8051 accesses external memory, port 2 outputs the upper byte of the 16-bit address, while port 0 carries the lower byte multiplexed with data.

The data byte D₀-D₇ and the lower address A₀-A₇ are the alternate functions of port 0. Serial input and output (RXD, TXD) are alternate functions of port 3.

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On power up, the 8051 uses following locations in the RAM for registers R_o - R_I and bit addressable memory :

A.00 - 2F and 2F - 30
B.00 - 7F and 7F - FF
C.00 - 07 and 20 - 2F
D.30 - 7F and 20 - 2F

Exam Year(s)

MH SET - 2021, SET Exam - 2021,

Answer: C

The locations are 00 - 07 and 20 - 2F.

On reset the 8051 selects register bank 0, so R0-R7 (printed R_o - R_I) occupy internal RAM addresses 00H to 07H. Banks 1 to 3 follow up to 1FH. The bit-addressable area is the 16 bytes from 20H to 2FH, giving 128 individually addressable bits, and the general-purpose scratch area runs from 30H to 7FH.

00-7F is the whole lower internal RAM and 80-FF holds the special function registers. 30-7F is the scratch area, not the register bank.

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After reset, SP register in 8051 is initialized to address .............. .

A.8 H
B.9 H
C.7 H
D.6 H

Exam Year(s)

MH SET - 2023, SET Exam - 2023,

Answer: C

After reset, SP is initialised to 07H.

On reset, the 8051 loads the stack pointer with 07H. Because the 8051 increments SP before it stores data, the first byte pushed goes to location 08H, the start of register bank 1. Programs that use banks 1 to 3 usually move the stack higher.

08H is where the first pushed byte lands, not the reset value of SP. 09H and 06H have no special role at reset.

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10.

What is the address range of SFR Register bank ?

A.00H - 77H
B.40H - 80H
C.80H - 7FH
D.80H - FFH

Exam Year(s)

MH SET - 2023, SET Exam - 2023,

Answer: B

The SFR address range is 80H - FFH.

In the 8051 the special function registers, such as the accumulator, B, PSW, SP, DPTR, the port latches and the timer and serial registers, occupy the upper 128 bytes of the direct address space, 80H to FFH. Only some of these addresses are actually used.

00H to 7FH is the internal RAM (register banks, bit-addressable area and scratch pad), so 00H - 77H is part of RAM. 40H - 80H straddles RAM and the SFRs, and 80H - 7FH is not a valid range.

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8051 Microcontroller Architecture Questions and Answers

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