Multiplexers and Decoders Questions and Answers

Q: For 3 : 8 decoder, the LED will be switched on for :

The LED is on for \(\bar{C}\bar{B}A + \bar{C}BA + C\bar{B}\bar{A} + CB\bar{A}\).The decoder outputs are active-low, and y0, y2, y5 and y7 feed the NAND gate. A NAND of active-low signals acts as an OR of the selected minterms, so\[ F = m_{0} + m_{2} + m_{5} + m_{7} \]The LED has its anode at +VCC and its cathode at F, so it lights only when F is LOW, that is for the remaining minterms m1, m3, m4 and m6. With C as the most significant bit these are 001, 011, 100 and 110, the four terms of the third option.The other options include terms such as CBA (m7) or \(\bar{C}B\bar{A}\) (m2), for which F is HIGH and the LED is off.

Q: Number of 2-input multiplexers required to construct a \(2^{10}\) input multiplexer is :

The number of 2-input multiplexers is 1023.A tree of 2-to-1 multiplexers halves the number of lines at each level. For \(2^{10} = 1024\) inputs the levels hold 512, 256, 128 and so on down to 1 multiplexer:\[ \begin{aligned} N &= 512 + 256 + \dots + 2 + 1 \\ &= 2^{10} - 1 = 1023 \end{aligned} \]In general an n-input multiplexer needs n - 1 two-input multiplexers. 9 is the number of select lines short by one (there are 10 levels), and 32 and 128 count only part of the tree.

Q: For design of 16 : 1 MUX how many select lines are required ?

A 16 : 1 multiplexer needs 4 select lines.Each select line is a binary digit, and \(n\) select lines can address \(2^{n}\) different inputs. We need the smallest \(n\) with\[ 2^{n} = 16 \Rightarrow n = \log_{2} 16 = 4 \]The four lines S3 S2 S1 S0 run from 0000 to 1111 and pick inputs I0 to I15.One select line serves a 2 : 1 MUX, two serve a 4 : 1 and three serve an 8 : 1, so 1, 2 and 3 are each too few for sixteen inputs.

Q: A decoder converts 'n' inputs to ......... outputs.

A decoder converts \(n\) inputs to \(2^{n}\) outputs.An \(n\)-bit input can take \(2^{n}\) distinct combinations, and a full binary decoder has one output line for each, with exactly one output active for any input code. A 2-to-4 decoder has 2 inputs and 4 outputs, a 3-to-8 decoder 3 inputs and 8 outputs, and a 4-to-16 decoder 4 inputs and 16 outputs.\(n\) outputs would mean only one per input, which is not decoding. \(n^{2}\) happens to equal \(2^{n}\) at \(n = 2\) and \(n = 4\) but not in general (for \(n = 3\) it gives 9 rather than 8), and \(n^{n}\) grows far faster than the number of possible input codes.

Q: ................. is an example of a combinational circuit.

Multiplexers are combinational circuits.A combinational circuit's output depends only on its present inputs. A multiplexer simply routes one of its data inputs to the output according to the select inputs, with no memory, so it is combinational. Adders, decoders, encoders and comparators are other examples.Shift registers, counters and flip-flops are sequential circuits: their outputs depend on stored state as well as on present inputs, and flip-flops are the memory elements from which registers and counters are built.

11.

For 3 : 8 decoder, the LED will be switched on for :

3 to 8 decoder with inputs A B C, enable tied to 1 and active-low outputs y0 to y7; y0 y2 y5 y7 feed a NAND gate whose output F drives an LED from +VCC

A.\(C B A + \bar{C} B A + C \bar{B} \bar{A} + C B \bar{A}\)
B.\(\bar{C} B \bar{A} + \bar{C} B A + C B \bar{A} + \bar{C} \bar{B} \bar{A}\)
C.\(\bar{C} \bar{B} A + \bar{C} B A + C \bar{B} \bar{A} + C B \bar{A}\)
D.\(\bar{C} \bar{B} A + C B A + C \bar{B} \bar{A} + C B \bar{A}\)

Exam Year(s)

MH SET - 2021, SET Exam - 2021,

Answer: C

The LED is on for \(\bar{C}\bar{B}A + \bar{C}BA + C\bar{B}\bar{A} + CB\bar{A}\).

The decoder outputs are active-low, and y₀, y₂, y₅ and y₇ feed the NAND gate. A NAND of active-low signals acts as an OR of the selected minterms, so

\[ F = m_{0} + m_{2} + m_{5} + m_{7} \]

The LED has its anode at +V_CC and its cathode at F, so it lights only when F is LOW, that is for the remaining minterms m₁, m₃, m₄ and m₆. With C as the most significant bit these are 001, 011, 100 and 110, the four terms of the third option.

The other options include terms such as CBA (m₇) or \(\bar{C}B\bar{A}\) (m₂), for which F is HIGH and the LED is off.

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12.

Number of 2-input multiplexers required to construct a \(2^{10}\) input multiplexer is :

A.32
B.9
C.128
D.1023

Exam Year(s)

MH SET - 2023, SET Exam - 2023,

Answer: D

The number of 2-input multiplexers is 1023.

A tree of 2-to-1 multiplexers halves the number of lines at each level. For \(2^{10} = 1024\) inputs the levels hold 512, 256, 128 and so on down to 1 multiplexer:

\[ \begin{aligned} N &= 512 + 256 + \dots + 2 + 1 \\ &= 2^{10} - 1 = 1023 \end{aligned} \]

In general an n-input multiplexer needs n - 1 two-input multiplexers. 9 is the number of select lines short by one (there are 10 levels), and 32 and 128 count only part of the tree.

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13.

For design of 16 : 1 MUX how many select lines are required ?

Exam Year(s)

MH SET - 2024, SET Exam - 2024,

Answer: D

A 16 : 1 multiplexer needs 4 select lines.

Each select line is a binary digit, and \(n\) select lines can address \(2^{n}\) different inputs. We need the smallest \(n\) with

\[ 2^{n} = 16 \Rightarrow n = \log_{2} 16 = 4 \]

The four lines S3 S2 S1 S0 run from 0000 to 1111 and pick inputs I0 to I15.

One select line serves a 2 : 1 MUX, two serve a 4 : 1 and three serve an 8 : 1, so 1, 2 and 3 are each too few for sixteen inputs.

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14.

A decoder converts 'n' inputs to ......... outputs.

A.\(n\)
B.\(n^{2}\)
C.\(2^{n}\)
D.\(n^{n}\)

Exam Year(s)

MH SET - 2024, SET Exam - 2024,

Answer: C

A decoder converts \(n\) inputs to \(2^{n}\) outputs.

An \(n\)-bit input can take \(2^{n}\) distinct combinations, and a full binary decoder has one output line for each, with exactly one output active for any input code. A 2-to-4 decoder has 2 inputs and 4 outputs, a 3-to-8 decoder 3 inputs and 8 outputs, and a 4-to-16 decoder 4 inputs and 16 outputs.

\(n\) outputs would mean only one per input, which is not decoding. \(n^{2}\) happens to equal \(2^{n}\) at \(n = 2\) and \(n = 4\) but not in general (for \(n = 3\) it gives 9 rather than 8), and \(n^{n}\) grows far faster than the number of possible input codes.

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15.

................. is an example of a combinational circuit.

A.Shift Registers
B.Counters
C.Flip flops
D.Multiplexers

Exam Year(s)

MH SET - 2025, SET Exam - 2025,

Answer: D

Multiplexers are combinational circuits.

A combinational circuit's output depends only on its present inputs. A multiplexer simply routes one of its data inputs to the output according to the select inputs, with no memory, so it is combinational. Adders, decoders, encoders and comparators are other examples.

Shift registers, counters and flip-flops are sequential circuits: their outputs depend on stored state as well as on present inputs, and flip-flops are the memory elements from which registers and counters are built.

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16.

The output f of the 4-to-1 Mux shown in the given figure is

A 4-to-1 multiplexer with data inputs 3, 2 and 1 tied to Vcc, data input 0 tied to ground, select lines x and y at the bottom and output f

A.\(\overline{xy} + x\)
B.\(x + y\)
C.\(\overline{x} + \overline{y}\)
D.\(x\overline{y}\)

Exam Year(s)

UGC NET - 2012,

Answer: B

The multiplexer output is \(x + y\) (option B). Data inputs 1, 2 and 3 are tied to \(V_{CC}\) (logic 1) and input 0 is grounded (logic 0), so the output is 0 only when the select lines choose input 0, that is x = 0 and y = 0, and it is 1 for every other combination. That is the OR function.

\[ f = \overline{x}\,\overline{y}\cdot 0 + \overline{x}y\cdot 1 \]

\[ \quad + x\overline{y}\cdot 1 + xy\cdot 1 = x + y \]

Options A and C are 1 for most or all inputs, and option D, \(x\overline{y}\), is 1 for only one combination, so none of them matches the OR behaviour.

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17.

Match List – I with List – II and select the correct answer by using the codes given below the lists :

List – I	List – II
a. Multiplexer	1. Sequential memory
b. De-multiplexer	2. Converts decimal number to binary
c. Shift-register	3. Data Selection
d. Encoder	4. Routes out many data input with single data output

Codes : a b c d

A.3 4 1 2
B.4 3 1 2
C.3 4 2 1
D.1 2 3 4

Exam Year(s)

UGC NET - 2012,

Answer: B

The key matches the multiplexer with the item that routes many data inputs to a single data output, so a matches 4, and the de-multiplexer with data selection, so b matches 3. The shift register is a sequential memory, so c matches 1, and the encoder converts a decimal number into binary, so d matches 2. The code is 4 3 1 2. The first option, 3 4 1 2, interchanges the first two pairs, which would call the multiplexer the data selection element and the de-multiplexer the many-to-one device, and the key does not accept that. The answer is 4 3 1 2, as the key has it.

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18.

Consider the below circuit and find the output function f(x, y, z).

A circuit of two 2-to-1 multiplexers. The first has x on input 0, not-y on input 1 and z as the select line. Its output goes to input 0 of the second multiplexer, whose input 1 is x and whose select line is y; the second output is f.

A.\(x\overline{z} + xy + \overline{y}z\)
B.\(x\overline{z} + xy + \overline{y}\,\overline{z}\)
C.\(xz + xy + \overline{y}\,\overline{z}\)
D.\(xz + x\overline{y} + \overline{y}z\)

Exam Year(s)

UGC NET - 2012,

Answer: A

The first multiplexer has z as its select line, with x on input 0 and the complement of y on input 1, so its output is \(\overline{z}x + z\overline{y}\). The second has y as its select line, with the first output on input 0 and x on input 1, so

\[ f = \overline{y}(x\overline{z} + \overline{y}z) + yx \]

\[ f = x\overline{y}\,\overline{z} + \overline{y}z + xy \]

\[ f = x\overline{z} + xy + \overline{y}z \]

The first two terms with x combine, since \(\overline{y}\,\overline{z} + y = \overline{z} + y\). So the output is option (A).

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19.

Match the following lists :

List - I	List - II
(a) 74150	(i) Quad 2 : 1 Multiplexer
(b) 74152	(ii) Dual 4 : 1 Multiplexer
(c) 74153	(iii) 8 : 1 Multiplexer
(d) 74157	(iv) 16 : 1 Multiplexer

Codes :
(a) (b) (c) (d)

A.(i) (ii) (iii) (iv)
B.(iv) (iii) (ii) (i)
C.(iv) (ii) (iii) (i)
D.(ii) (i) (iv) (iii)

Exam Year(s)

UGC NET - 2013,

Answer: B

The correct match is a-iv, b-iii, c-ii, d-i, the second option. The 74150 is a 16:1 multiplexer, the 74152 is an 8:1 multiplexer, the 74153 is a dual 4:1 multiplexer, and the 74157 is a quad 2:1 multiplexer.

The other options give a wrong size to at least one chip, for example the first assigns the quad 2:1 type to the 74150, which has sixteen inputs. The chip numbers are the standard TTL data selector series, where the digit group after 741 shows the size of the selector.

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20.

List - I	List - II
a. 8031	i. Multiplexer
b. 7490	ii. Demultiplexer
c. 74155	iii. Microcontroller
d. 74151	iv. Decade counter

Codes : a b c d

A.iii iv ii i
B.i ii iii iv
C.ii iii iv i
D.iii i ii iv

Exam Year(s)

UGC NET - 2013,

Answer: A

The correct matching is a-iii, b-iv, c-ii, d-i, which is code (A).

The 8031 is a microcontroller (iii), the 7490 is a decade counter (iv), the 74155 is a dual 2-to-4 decoder or demultiplexer (ii) and the 74151 is an 8-to-1 multiplexer (i).

Codes (B), (C) and (D) give at least one chip the wrong function, for example the 74151 as a demultiplexer.

The numbers in the 74 series follow the function: the 7490 counts in decimal by dividing by 2 and by 5, and the multiplexer chooses one of eight inputs with three select lines, while the decoder or demultiplexer sends one input to one of four outputs. The 8031 is the ROM-less member of the 8051 family.

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