Logic Families Questions and Answers

Q: Which equation is correct for a digital gate with symbols carrying usual meaning ?

The correct equation is \(V_{NH} = V_{0H(Min)} - V_{1H(Min)}\), where the paper prints 0 and 1 for the O (output) and I (input) of \(V_{OH}\) and \(V_{IH}\).The high-level noise margin is the gap between the lowest guaranteed high output of one gate and the lowest input the next gate still reads as high. Similarly the low-level margin is \(V_{NL} = V_{IL(Max)} - V_{OL(Max)}\).Options A and B add the levels instead of subtracting them, and option C mixes the high-level output with the low-level margin. For standard TTL, for example, \(V_{OH(Min)} = 2.4\) V and \(V_{IH(Min)} = 2.0\) V give a high noise margin of 0.4 V.

Q: Propagation delay of logic families in descending order can be listed as :

In descending order of propagation delay the families are CMOS, TTL, ECL.Standard CMOS (the 4000 series) is the slowest of the three, with delays of tens of nanoseconds, because its high-impedance transistors charge load capacitance slowly. Standard TTL is faster, about 10 ns per gate. ECL is the fastest, around 1 ns or less, because its transistors never saturate and so do not have to clear stored charge before switching.The options beginning with ECL list the fastest family first, which is ascending order, and the option starting with TTL puts ECL in the middle.

For the given logic family, if all the inputs (A, B) are high, then output Z will be:

Totem-pole TTL gate circuit with a multi-emitter input transistor T1 (RB1 4 kilohm) at inputs A and B, T2 (RC2 1.6 kilohm, RE2 1 kilohm), output transistor T3 (RC3 100 ohm) with diode D, and T4 to ground, output Z, supply +5 V

A.0
B.1
C.AB
D.A'+B

Exam Year(s)

DSSSB AE - 2023,

Answer: A

The circuit is a TTL NAND gate with a totem pole output: a multi-emitter input transistor T1, a phase splitter T2, and the output pair T3 (with the diode D) and T4.

When all the inputs A and B are high, the base collector junction of T1 conducts, so current from the supply through the 4 kilohm resistor flows into the base of T2, which turns on and in turn drives T4 into saturation. The emitter voltage of T2 turns T4 on while the voltage at the collector of T2 falls too low to keep T3 and the diode conducting, so T3 is off. The output Z is pulled to ground through the saturated T4, so Z is low, logic 0.

That is the NAND gate action: the output is low only when all the inputs are high. The answer is 0, option A.

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Which equation is correct for a digital gate with symbols carrying usual meaning ?

A.\(V_{NL} = V_{1L(Max)} + V_{0L(Max)}\)
B.\(V_{NH} = V_{0H(Min)} + V_{1H(Min)}\)
C.\(V_{NL} = V_{0H(Min)} - V_{1H(Min)}\)
D.\(V_{NH} = V_{0H(Min)} - V_{1H(Min)}\)

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: D

The correct equation is \(V_{NH} = V_{0H(Min)} - V_{1H(Min)}\), where the paper prints 0 and 1 for the O (output) and I (input) of \(V_{OH}\) and \(V_{IH}\).

The high-level noise margin is the gap between the lowest guaranteed high output of one gate and the lowest input the next gate still reads as high. Similarly the low-level margin is \(V_{NL} = V_{IL(Max)} - V_{OL(Max)}\).

Options A and B add the levels instead of subtracting them, and option C mixes the high-level output with the low-level margin. For standard TTL, for example, \(V_{OH(Min)} = 2.4\) V and \(V_{IH(Min)} = 2.0\) V give a high noise margin of 0.4 V.

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Propagation delay of logic families in descending order can be listed as :

A.ECL, TTL, CMOS
B.TTL, ECL, CMOS
C.CMOS, TTL, ECL
D.ECL, CMOS, TTL

Exam Year(s)

MH SET - 2021, SET Exam - 2021,

Answer: C

In descending order of propagation delay the families are CMOS, TTL, ECL.

Standard CMOS (the 4000 series) is the slowest of the three, with delays of tens of nanoseconds, because its high-impedance transistors charge load capacitance slowly. Standard TTL is faster, about 10 ns per gate. ECL is the fastest, around 1 ns or less, because its transistors never saturate and so do not have to clear stored charge before switching.

The options beginning with ECL list the fastest family first, which is ascending order, and the option starting with TTL puts ECL in the middle.

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