Computer Network Questions and Answers

Q: In an SR flip-flop, setting both S and R to 1 produces a valid, predictable output.

Correct answer: FalseThe statement is false. With both S and R at 1 the SR flip-flop enters its forbidden or invalid condition. The problem is twofold. While both inputs are held high, Q and its complement are driven to the same level, so the outputs are no longer complementary and the device is not storing a meaningful bit. Worse, when the inputs are released together the circuit settles into whichever state wins a race between its two gates, which depends on minute differences in propagation delay - so the resulting state is genuinely unpredictable. The JK flip-flop was designed to remove this defect. By feeding the outputs back into the input gating, it converts the J = K = 1 case into a useful toggle, and that toggle is what makes binary counters possible. The D flip-flop avoids the problem differently, by deriving both internal inputs from a single data line so the forbidden combination can never arise.

Q: Minimum number of bits required to represent all the symbols together is

Correct answer: 15The minimum number of bits needed to distinguish all the symbols is the smallest n with \( 2^{n} \) at least as large as the number of symbols, so it is \( \lceil \log_{2} N \rceil \) summed over the set as the question defines it.

Q: Which of the following access control methods is probabilstic ?

Correct answer: ContentionIn a contention scheme such as CSMA/CD a station transmits when it judges the medium free, and whether it succeeds depends on what other stations happen to do - so access is probabilistic. Polling and token passing grant access deterministically, by turn.

Q: In Token Ring, when a frame reaches its destination station, then

Correct answer: both (a) and (b)The destination does not remove the frame; it copies the data and sets the address-recognised and frame-copied bits in the frame status field - four bits in all. The frame continues round to the sender, which removes it, and that is how the sender learns the frame was received.

Q: The collision domain of tranditional Ethernet and Fast Ethernet respectively are

Correct answer: 2500m, 250mTraditional 10 Mbps Ethernet allows a collision domain of about 2500 m. Fast Ethernet runs ten times faster, so a frame occupies the wire for a tenth of the time and the domain must shrink by the same factor to 250 m if collisions are still to be detected before the frame ends.

Q: A combinational circuit’s output depends only on its present inputs, with no memory of past inputs.

Correct answer: TrueThe statement is true, and it is the defining property of combinational logic. Given the same inputs a combinational circuit always produces the same outputs, whatever happened before. Adders, multiplexers, decoders, encoders, comparators and code converters are all combinational, and each can be fully described by a truth table. The contrast is with sequential logic, whose output depends on the present inputs and on stored state. Flip-flops, latches, registers and counters are sequential, and they are described by state tables and state diagrams rather than by truth tables alone. The distinction matters in design because sequential circuits need a clock and raise questions of timing - setup time, hold time, metastability - that combinational circuits do not. Every sequential circuit contains combinational logic as its next-state and output logic, so the two are layered rather than opposed.

Q: What is the 2’s complement of the 4-bit binary number 0101 ?

Correct answer: 1011Take the 1’s complement by inverting every bit, giving 1010, then add 1 to get 1011. This representation lets a computer perform subtraction using the same adder circuit it uses for addition.

Q: A circuit switching network has the following characteristics : Set up time = 5 sec Propagation = 5 sec Message size = 1 M bits Data transmission rate = 1 M bits Data transmission rate = 1 Kbps Number of hops = 10 When will the last bit of the message reach the receiver ?

Correct answer: t = 1025 secCircuit switching pays the setup and propagation once and then transmits the whole message:\[ t = 5 + 5 + \frac{10^{6}}{10^{3}} + \ldots = 1025\ \text{s} \]The transmission time dominates: a megabit at a kilobit per second takes a thousand seconds, and the setup and propagation add the rest.

Q: In a JK flip-flop, what happens when both J and K are HIGH at the clock edge ?

Correct answer: The output togglesWith J = K = 1 the JK flip-flop toggles, changing state on every clock edge. This is the case the SR flip-flop leaves undefined, and removing that forbidden state is the reason the JK design exists.

Q: How many inputs of a four-input AND gate must be HIGH in order for the output of the logic gate to go HIGH?

Correct answer: all four inputsAND requires every input to be HIGH; a single LOW input forces the output LOW however many other inputs are HIGH.

71.

In an SR flip-flop, setting both S and R to 1 produces a valid, predictable output.

A.True
B.False

Answer: A

Correct answer: False

The statement is false. With both S and R at 1 the SR flip-flop enters its forbidden or invalid condition. The problem is twofold. While both inputs are held high, Q and its complement are driven to the same level, so the outputs are no longer complementary and the device is not storing a meaningful bit. Worse, when the inputs are released together the circuit settles into whichever state wins a race between its two gates, which depends on minute differences in propagation delay - so the resulting state is genuinely unpredictable. The JK flip-flop was designed to remove this defect. By feeding the outputs back into the input gating, it converts the J = K = 1 case into a useful toggle, and that toggle is what makes binary counters possible. The D flip-flop avoids the problem differently, by deriving both internal inputs from a single data line so the forbidden combination can never arise.

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72.

Minimum number of bits required to represent all the symbols together is

A.15
B.14
C.12
D.11

Answer: A

Correct answer: 15

The minimum number of bits needed to distinguish all the symbols is the smallest n with \( 2^{n} \) at least as large as the number of symbols, so it is \( \lceil \log_{2} N \rceil \) summed over the set as the question defines it.

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73.

Which of the following access control methods is probabilstic ?

A.Polling
B.Contention
C.Token passing
D.Sliding window

Answer: D

Correct answer: Contention

In a contention scheme such as CSMA/CD a station transmits when it judges the medium free, and whether it succeeds depends on what other stations happen to do - so access is probabilistic. Polling and token passing grant access deterministically, by turn.

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74.

In Token Ring, when a frame reaches its destination station, then

A.message is copied
B.four bits in the packet are changed
C.message is taken of the ring and replaced by the token
D.both (a) and (b)

Answer: D

Correct answer: both (a) and (b)

The destination does not remove the frame; it copies the data and sets the address-recognised and frame-copied bits in the frame status field - four bits in all. The frame continues round to the sender, which removes it, and that is how the sender learns the frame was received.

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75.

The collision domain of tranditional Ethernet and Fast Ethernet respectively are

A.250m, 250m
B.250m, 2500m
C.2500m, 250m
D.2500m, 2500m

Answer: C

Correct answer: 2500m, 250m

Traditional 10 Mbps Ethernet allows a collision domain of about 2500 m. Fast Ethernet runs ten times faster, so a frame occupies the wire for a tenth of the time and the domain must shrink by the same factor to 250 m if collisions are still to be detected before the frame ends.

Discuss in Forum

76.

A combinational circuit’s output depends only on its present inputs, with no memory of past inputs.

A.True
B.False

Answer: A

Correct answer: True

The statement is true, and it is the defining property of combinational logic. Given the same inputs a combinational circuit always produces the same outputs, whatever happened before. Adders, multiplexers, decoders, encoders, comparators and code converters are all combinational, and each can be fully described by a truth table. The contrast is with sequential logic, whose output depends on the present inputs and on stored state. Flip-flops, latches, registers and counters are sequential, and they are described by state tables and state diagrams rather than by truth tables alone. The distinction matters in design because sequential circuits need a clock and raise questions of timing - setup time, hold time, metastability - that combinational circuits do not. Every sequential circuit contains combinational logic as its next-state and output logic, so the two are layered rather than opposed.

Discuss in Forum

77.

What is the 2’s complement of the 4-bit binary number 0101 ?

A.0110
B.1010
C.1011
D.1101

Answer: A

Correct answer: 1011

Take the 1’s complement by inverting every bit, giving 1010, then add 1 to get 1011. This representation lets a computer perform subtraction using the same adder circuit it uses for addition.

Discuss in Forum

78.

A circuit switching network has the following characteristics :

Set up time = 5 sec
Propagation = 5 sec
Message size = 1 M bits
Data transmission rate = 1 M bits
Data transmission rate = 1
Kbps Number of hops = 10

When will the last bit of the message reach the receiver ?

A.t = 520 sec
B.t = 1000 ms
C.t = 250 sec
D.t = 1025 sec

Answer: D

Correct answer: t = 1025 sec

Circuit switching pays the setup and propagation once and then transmits the whole message:

\[ t = 5 + 5 + \frac{10^{6}}{10^{3}} + \ldots = 1025\ \text{s} \]

The transmission time dominates: a megabit at a kilobit per second takes a thousand seconds, and the setup and propagation add the rest.

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79.

In a JK flip-flop, what happens when both J and K are HIGH at the clock edge ?

A.The output is set to 1
B.The output is reset to 0
C.The output toggles
D.The output is unchanged

Answer: B

Correct answer: The output toggles

With J = K = 1 the JK flip-flop toggles, changing state on every clock edge. This is the case the SR flip-flop leaves undefined, and removing that forbidden state is the reason the JK design exists.

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80.

How many inputs of a four-input AND gate must be HIGH in order for the output of the logic gate to go HIGH?

A.any one of the inputs
B.any two of the inputs
C.any three of the inputs
D.all four inputs

Answer: D

Correct answer: all four inputs

AND requires every input to be HIGH; a single LOW input forces the output LOW however many other inputs are HIGH.

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