Pipelining Questions and Answers

Q: Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?

The dependence that causes a data hazard is Read-after-write.In a read-after-write (true) dependence, a later instruction reads a register that an earlier instruction writes. In a pipeline the later instruction can reach its operand-read stage before the earlier one has written its result back, so it would read a stale value unless the pipeline stalls or forwards the result.Read-after-read never causes a hazard, because reading does not change the register. Write-after-read and write-after-write are name dependences: in the standard in-order pipeline, where every instruction reads early and writes in the last stage in program order, they cannot go wrong. They become hazards only in pipelines that let instructions complete out of order, where register renaming removes them.

Q: An instruction format has the following structure:Instruction Number: Opcode destination reg, source reg-1, source reg-2Consider the following sequence of instructions to be executed in a pipelined processor:I1: DIV R3, R1, R2I2: SUB R5, R3, R4I3: ADD R3, R5, R6I4: MUL R7, R3, R8Which of the following statements is/are TRUE?

Only the first statement is true: There is a RAW dependency on R3 between I1 and I2.I1 writes R3 and I2 then reads R3, so I2 must wait for I1's result: a read-after-write (true) dependency.The other three name the wrong kind of hazard. Between I1 and I3 both instructions write R3, which is write-after-write (WAW), not WAR. Between I2 and I3, I2 reads R3 and I3 later writes it, which is write-after-read (WAR), not RAW. Between I3 and I4, I3 writes R3 and I4 reads it, which is RAW, not WAW.

Q: An 8086 microprocessor can fatch and Pre-fetch upto.......... bytes of instructions and stores them in the queue :

The 8086 can prefetch up to 6 bytes.The 8086's bus interface unit fetches instruction bytes ahead of time while the execution unit is busy and stores them in a 6-byte first-in first-out instruction queue. This overlap of fetching and executing is a simple form of pipelining.8 bytes is not the 8086 figure (its 8-bit-bus sibling, the 8088, has a 4-byte queue), and 16 and 20 bytes confuse the queue with the 16-bit data bus and the 20-bit address bus.

Q: Assume that an instruction pipeline has 5 stages without any branch prediction. Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO) with state delays as 6, 8, 6, 5 and 4 ns respectively.Consider a program with 15 instructions (I1 .... I15) where only I7 is a branch instruction and I12 is the target instruction.If the branch is taken during execution of the program then what is the time needed to complete the program ?

The program takes 144ns.A pipeline's clock must suit its slowest stage, so the cycle time is 8 ns. Because the branch I7 is taken to I12, only I1 to I7 and I12 to I15 are completed: 11 instructions.With no branch prediction, the outcome is known only when I7 reaches Execute (stage 4). The three instructions fetched after it (I8, I9, I10) are flushed, a penalty of 3 cycles.\[ \begin{aligned} \text{cycles} &= (k - 1) + n + \text{penalty} \\ &= 4 + 11 + 3 = 18 \\ \text{time} &= 18 \times 8 = 144\ \text{ns} \end{aligned} \]Running all 15 instructions without the branch would take (4 + 15) x 8 = 152 ns. 210 and 216 ns ignore pipelining, and 25 ns is a single instruction's latency without the common clock.

Q: In a 5-stage pipeline, branch is resolved in EX stage. If branch frequency = 15% and misprediction penalty = 2 cycles, what is pipeline CPI?

The pipeline CPI is 1.3.An ideal 5-stage pipeline completes one instruction per cycle, CPI = 1. Each branch resolved in EX costs 2 stall cycles, and 15% of instructions are branches:\[ \begin{aligned} \text{CPI} &= 1 + f_{branch} \times \text{penalty} \\ &= 1 + 0.15 \times 2 = 1.3 \end{aligned} \]The other values imply different branch rates: 1.1 would mean 5% branches, 1.2 would mean 10% and 1.4 would mean 20% at the same 2-cycle penalty. The question treats every branch as paying the 2-cycle penalty, which is what resolving branches in EX without prediction means.

Q: In a 4-stage pipeline (Fetch, Decode, Execute, Write-back), if each stage takes 10 ns, what is the throughput after the pipeline is full (instructions per second) ?

The throughput is 100 million instructions per second.Once the pipeline is full, one instruction completes every clock cycle, and the cycle equals the stage time of 10 ns:\[ \begin{aligned} \text{throughput} &= \frac{1}{10\ \text{ns}} \\ &= \frac{1}{10 \times 10^{-9}\ \text{s}} = 10^{8}\ \text{per s} \end{aligned} \]25 million is what an unpipelined processor would manage, one instruction every 40 ns (four stages of 10 ns). The number of stages sets the latency of each instruction, not the rate at which they finish once the pipeline is full.

Q: Consider an instruction pipeline with four stages (S1, S2, S3 and S4), each with a combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers are as given in the following figure :What is the approximate speed up of the pipeline in steady state under ideal conditions when compared to the corresponding non-pipeline implementation ?

The speed-up is about 2.5.Without pipelining one instruction takes the sum of the stage delays. With pipelining the clock must fit the slowest stage plus its register delay:\[ \begin{aligned} T_{non} &= 5 + 6 + 11 + 8 = 30\ \text{ns} \\ T_{pipe} &= 11 + 1 = 12\ \text{ns} \\ S &= 30 / 12 = 2.5 \end{aligned} \]4.0 is the ideal speed-up for four equal stages, which these stages are not. Even ignoring the register delay gives only 30/11, about 2.7, so 3.0 is too high, and 1.1 matches nothing.

Q: Which of the following are NOT true in a pipelined processor ?I. Bypassing can handle all RAW hazards.II. Register renaming can eliminate all register carried WAR hazards.III. Control hazard penalties can be eliminated by dynamic branch prediction.

The statements that are NOT true are I and III only.Statement I is false: forwarding (bypassing) cannot remove every read-after-write hazard. When an instruction needs a value being loaded from memory by the instruction just before it, the data arrives too late to forward, and the pipeline must stall.Statement III is false: dynamic branch prediction reduces control hazard penalties, but mispredictions still occur and cost cycles, so the penalty cannot be eliminated.Statement II is true: write-after-read and write-after-write hazards on registers are name dependences, and renaming each destination to a fresh physical register removes them. So any option including II is wrong.

Q: Register renaming is done in pipelined processors

Register renaming is done to handle certain kinds of hazards.Renaming maps the architectural registers named in instructions onto a larger set of physical registers, giving each new result its own register. This removes write-after-read and write-after-write hazards, which arise only because two instructions happen to reuse the same register name, and lets the processor execute such instructions out of order.It is done in hardware at run time, so it is not an alternative to the compiler's register allocation, it has nothing to do with accessing parameters and local variables, and it is not part of virtual-to-physical address translation.

Q: In a pipelined processor, what is the main cause of a control hazard ?

The main cause of a control hazard is branch instructions.A pipeline fetches the next instruction before the current one has finished. When the current instruction is a branch or jump, the processor does not know which instruction comes next until the branch is resolved, so the instructions already fetched may be the wrong ones and must be flushed. That stall is a control (branch) hazard, reduced by branch prediction and delayed branching.A data dependency, where one instruction needs the result of an earlier one, causes a data hazard. Memory latency and cache misses cause stalls too, but they are not what defines a control hazard.

Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?

A.Read-after-read
B.Read-after-write
C.Write-after-read
D.Write-after-write

Exam Year(s)

GATE CS - 2026,

Answer: B

The dependence that causes a data hazard is Read-after-write.

In a read-after-write (true) dependence, a later instruction reads a register that an earlier instruction writes. In a pipeline the later instruction can reach its operand-read stage before the earlier one has written its result back, so it would read a stale value unless the pipeline stalls or forwards the result.

Read-after-read never causes a hazard, because reading does not change the register. Write-after-read and write-after-write are name dependences: in the standard in-order pipeline, where every instruction reads early and writes in the last stage in program order, they cannot go wrong. They become hazards only in pipelines that let instructions complete out of order, where register renaming removes them.

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An instruction format has the following structure:

Instruction Number: Opcode destination reg, source reg-1, source reg-2

Consider the following sequence of instructions to be executed in a pipelined processor:

I1: DIV R3, R1, R2
I2: SUB R5, R3, R4
I3: ADD R3, R5, R6
I4: MUL R7, R3, R8

Which of the following statements is/are TRUE?

A.There is a RAW dependency on R3 between I1 and I2
B.There is a WAR dependency on R3 between I1 and I3
C.There is a RAW dependency on R3 between I2 and I3
D.There is a WAW dependency on R3 between I3 and I4

Exam Year(s)

GATE CS - 2024,

Answer: A

Only the first statement is true: There is a RAW dependency on R3 between I1 and I2.

I1 writes R3 and I2 then reads R3, so I2 must wait for I1's result: a read-after-write (true) dependency.

The other three name the wrong kind of hazard. Between I1 and I3 both instructions write R3, which is write-after-write (WAW), not WAR. Between I2 and I3, I2 reads R3 and I3 later writes it, which is write-after-read (WAR), not RAW. Between I3 and I4, I3 writes R3 and I4 reads it, which is RAW, not WAW.

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An 8086 microprocessor can fatch and Pre-fetch upto.......... bytes of instructions and stores them in the queue :

A.8
B.6
C.16
D.20

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: B

The 8086 can prefetch up to 6 bytes.

The 8086's bus interface unit fetches instruction bytes ahead of time while the execution unit is busy and stores them in a 6-byte first-in first-out instruction queue. This overlap of fetching and executing is a simple form of pipelining.

8 bytes is not the 8086 figure (its 8-bit-bus sibling, the 8088, has a 4-byte queue), and 16 and 20 bytes confuse the queue with the 16-bit data bus and the 20-bit address bus.

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Assume that an instruction pipeline has 5 stages without any branch prediction. Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO) with state delays as 6, 8, 6, 5 and 4 ns respectively.

Consider a program with 15 instructions (I₁ .... I₁₅) where only I₇ is a branch instruction and I₁₂ is the target instruction.

If the branch is taken during execution of the program then what is the time needed to complete the program ?

A.210ns
B.216ns
C.25ns
D.144ns

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: D

The program takes 144ns.

A pipeline's clock must suit its slowest stage, so the cycle time is 8 ns. Because the branch I7 is taken to I12, only I1 to I7 and I12 to I15 are completed: 11 instructions.

With no branch prediction, the outcome is known only when I7 reaches Execute (stage 4). The three instructions fetched after it (I8, I9, I10) are flushed, a penalty of 3 cycles.

\[ \begin{aligned} \text{cycles} &= (k - 1) + n + \text{penalty} \\ &= 4 + 11 + 3 = 18 \\ \text{time} &= 18 \times 8 = 144\ \text{ns} \end{aligned} \]

Running all 15 instructions without the branch would take (4 + 15) x 8 = 152 ns. 210 and 216 ns ignore pipelining, and 25 ns is a single instruction's latency without the common clock.

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In a 5-stage pipeline, branch is resolved in EX stage. If branch frequency = 15% and misprediction penalty = 2 cycles, what is pipeline CPI?

A.1.3
B.1.2
C.1.1
D.1.4

Exam Year(s)

Tripura Public Service Commission - 2026,

Answer: A

The pipeline CPI is 1.3.

An ideal 5-stage pipeline completes one instruction per cycle, CPI = 1. Each branch resolved in EX costs 2 stall cycles, and 15% of instructions are branches:

\[ \begin{aligned} \text{CPI} &= 1 + f_{branch} \times \text{penalty} \\ &= 1 + 0.15 \times 2 = 1.3 \end{aligned} \]

The other values imply different branch rates: 1.1 would mean 5% branches, 1.2 would mean 10% and 1.4 would mean 20% at the same 2-cycle penalty. The question treats every branch as paying the 2-cycle penalty, which is what resolving branches in EX without prediction means.

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In a 4-stage pipeline (Fetch, Decode, Execute, Write-back), if each stage takes 10 ns, what is the throughput after the pipeline is full (instructions per second) ?

A.25 million
B.50 million
C.100 million
D.200 million

Exam Year(s)

Tripura Public Service Commission - 2026,

Answer: C

The throughput is 100 million instructions per second.

Once the pipeline is full, one instruction completes every clock cycle, and the cycle equals the stage time of 10 ns:

\[ \begin{aligned} \text{throughput} &= \frac{1}{10\ \text{ns}} \\ &= \frac{1}{10 \times 10^{-9}\ \text{s}} = 10^{8}\ \text{per s} \end{aligned} \]

25 million is what an unpipelined processor would manage, one instruction every 40 ns (four stages of 10 ns). The number of stages sets the latency of each instruction, not the rate at which they finish once the pipeline is full.

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Consider an instruction pipeline with four stages (S1, S2, S3 and S4), each with a combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers are as given in the following figure :

Four pipeline stages in a row: S1 delay 5 ns, S2 delay 6 ns, S3 delay 11 ns and S4 delay 8 ns, each followed by a pipeline register with delay 1 ns

What is the approximate speed up of the pipeline in steady state under ideal conditions when compared to the corresponding non-pipeline implementation ?

A.4.0
B.2.5
C.1.1
D.3.0

Exam Year(s)

Tripura Public Service Commission - 2025,

Answer: B

The speed-up is about 2.5.

Without pipelining one instruction takes the sum of the stage delays. With pipelining the clock must fit the slowest stage plus its register delay:

\[ \begin{aligned} T_{non} &= 5 + 6 + 11 + 8 = 30\ \text{ns} \\ T_{pipe} &= 11 + 1 = 12\ \text{ns} \\ S &= 30 / 12 = 2.5 \end{aligned} \]

4.0 is the ideal speed-up for four equal stages, which these stages are not. Even ignoring the register delay gives only 30/11, about 2.7, so 3.0 is too high, and 1.1 matches nothing.

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Which of the following are NOT true in a pipelined processor ?

I. Bypassing can handle all RAW hazards.
II. Register renaming can eliminate all register carried WAR hazards.
III. Control hazard penalties can be eliminated by dynamic branch prediction.

A.I and II only
B.I and III only
C.II and III only
D.All of these

Exam Year(s)

Tripura Public Service Commission - 2025,

Answer: B

The statements that are NOT true are I and III only.

Statement I is false: forwarding (bypassing) cannot remove every read-after-write hazard. When an instruction needs a value being loaded from memory by the instruction just before it, the data arrives too late to forward, and the pipeline must stall.

Statement III is false: dynamic branch prediction reduces control hazard penalties, but mispredictions still occur and cost cycles, so the penalty cannot be eliminated.

Statement II is true: write-after-read and write-after-write hazards on registers are name dependences, and renaming each destination to a fresh physical register removes them. So any option including II is wrong.

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A.as an alternative to register allocation at compile time
B.for efficient access to function parameters and local variables
C.to handle certain kinds of hazards
D.as part of address translation

Exam Year(s)

Tripura Public Service Commission - 2025,

Answer: C

Renaming maps the architectural registers named in instructions onto a larger set of physical registers, giving each new result its own register. This removes write-after-read and write-after-write hazards, which arise only because two instructions happen to reuse the same register name, and lets the processor execute such instructions out of order.

It is done in hardware at run time, so it is not an alternative to the compiler's register allocation, it has nothing to do with accessing parameters and local variables, and it is not part of virtual-to-physical address translation.

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10.

In a pipelined processor, what is the main cause of a control hazard ?

A.Data dependency
B.Branch instructions
C.Memory latency
D.Cache miss

Exam Year(s)

Tripura Public Service Commission - 2026,

Answer: B

The main cause of a control hazard is branch instructions.

A pipeline fetches the next instruction before the current one has finished. When the current instruction is a branch or jump, the processor does not know which instruction comes next until the branch is resolved, so the instructions already fetched may be the wrong ones and must be flushed. That stall is a control (branch) hazard, reduced by branch prediction and delayed branching.

A data dependency, where one instruction needs the result of an earlier one, causes a data hazard. Memory latency and cache misses cause stalls too, but they are not what defines a control hazard.

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