Counters Questions and Answers

Answer: B

In a ripple counter each flipflop is clocked by the output of the one before it, so the delays add up. For four stages

\[ t_{total} = 4 \times 25\ \text{ns} = 100\ \text{ns} \]

The clock period must be at least the total delay, so the highest clock frequency is

\[ f = \frac{1}{100 \times 10^{-9}} = 10\ \text{MHz} \]

The value 100 MHz is the frequency for a single flipflop of 10 ns, and 1 MHz and 100 kHz are far below the limit. The answer is 10 MHz, option B.

Answer: D

A 4 bit counter counts in the binary sequence, each count adding one to the previous output. Starting at 0000, the outputs are 0001, 0010, 0011 and then 0100.

\[ 0000 \to 0001 \to 0010 \to 0011 \to 0100 \]

The value 0100 is the decimal number 4, so it takes 4 counts, whether the counter is asynchronous (ripple) or synchronous, since the sequence of the outputs is the same; the difference is in the timing. The answer is 4, option D.

Answer: D

A decade counter counts ten states, 0000 to 1001 (0 to 9), and then resets. The number of flip flops \(n\) must satisfy \(2^n \ge 10\).

\[ 2^3 = 8 \lt 10,\qquad 2^4 = 16 \ge 10 \]

So three flip flops give only 8 states, which is not enough, and four are needed. The counter is a mod 10 counter built with 4 JK flip flops and the extra states 1010 to 1111 are not used. The answer is 4, option D.

Answer: A

A ripple counter is a cascaded arrangement of flip-flops in which the output of one flip-flop drives the clock input of the next, so the change ripples through the chain. In a synchronous counter all flip-flops share one clock. A ring counter is a shift register whose last output is fed back to the first input. 'Cascaded counter' is not the standard name for this arrangement. It is called a ripple counter because the change in one stage moves on, stage by stage, like a ripple, and so it is also called an asynchronous counter.

Answer: A

The state that can never occur is (0, 0, 1).

All three flip-flops share CLKIN. From the figure, the first T input is \(\overline{Q3}\), the D input is Q1, and the second T input is Q2. So at each clock edge:

\[ \begin{aligned} Q1^{+} &= Q1 \oplus \overline{Q3} \\ Q2^{+} &= Q1 \\ Q3^{+} &= Q3 \oplus Q2 \end{aligned} \]

Starting from (0, 1, 1), the states run 011, 000, 100, 010, 101, 111, 110, and then back to 011. That cycle holds seven of the eight states; the missing one is 001.

(1, 0, 0) appears after the second clock, (1, 0, 1) after the fourth and (1, 1, 1) after the fifth, so they can all be obtained.

Answer: B

In a synchronous counter the clock is applied to the inputs of all flip-flops, that is, to the clock input of every flip-flop at once.

All flip-flops of a synchronous counter share one clock line and change state together on the same clock edge; gating logic on their J-K or D inputs decides which ones toggle. This removes the accumulated delay of a ripple counter.

In a ripple (asynchronous) counter, only the first flip-flop receives the external clock, and each later flip-flop is clocked by the output of the one before it, in cascade. The options about even or odd numbered flip-flops describe no real counter.

Answer: B

The conversion time is 512 μsec.

A counter-type ADC counts up from zero until the DAC output matches the input, so a full-scale conversion takes \( 2^{n} \) clock pulses. For 8 bits that is 256 pulses, and a 500 kHz clock has a period of 2 μs:

\[ \begin{aligned} t &= 2^{8} \times \frac{1}{500\ \text{kHz}} \\ &= 256 \times 2\ \mu\text{s} = 512\ \mu\text{s} \end{aligned} \]

256 μsec counts each pulse as 1 μs (a 1 MHz clock), and 1024 or 2048 μsec correspond to 9 or 10 bits.

Answer: A

The delay range is 0 to 64 mS with 1 µS resolution.

With a 1 MHz clock, each count lasts 1 µs, which is the resolution. A 16-bit presettable counter can be loaded with any count from 0 to \(2^{16} - 1\):

\[ \begin{aligned} 2^{16} &= 65536\ \text{counts} \\ T_{max} &= 65536 \times 1\ \mu s \\ &\approx 65.5\ \text{ms} \end{aligned} \]

Taking 64K (65,536) counts as '64 ms', the delay runs from 0 to about 64 ms in 1 µs steps. 16 µs confuses the number of bits with the count, and a 1 ms resolution would need a 1 kHz clock.

Answer: C

The times are 15 ns for the synchronous counter and 60 ns for the asynchronous counter.

In a synchronous counter every flip-flop is clocked at the same instant, so all outputs settle one propagation delay after the clock edge: 15 ns, however many stages there are.

In an asynchronous (ripple) counter each flip-flop is clocked by the output of the one before it, so in the worst case (for example 0111 to 1000) the change ripples through all four stages: 4 × 15 = 60 ns.

The 45 ns option counts only three stages, and the option giving 60 ns and 15 ns reverses the two counters.

Answer: D

The maximum delay per stage is 100 nsec.

A modulo-1024 counter needs \(2^{10} = 1024\), so ten flip-flops. In a ripple counter each flip-flop is clocked by the one before it, so in the worst case a change ripples through all ten stages, and the total delay must be less than one clock period:

\[ \begin{aligned} T &= \frac{1}{1\ \text{MHz}} = 1\ \mu\text{s} \\ 10\,t_{pd} &\le 1\ \mu\text{s} \\ t_{pd} &\le 100\ \text{ns} \end{aligned} \]

Delays of 10, 20 or 50 ns would also work, but the question asks for the maximum permissible value, which is 100 ns.