Three of the following can wake a device from deep sleep. The exception is
Answer: C
The DMA controller's clock is stopped along with almost everything else, so no transfer is in progress to complete. The real time clock, the wake pins and the independent watchdog all run from a low frequency oscillator that survives the mode.
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Clock gating saves power by
Answer: D
Correct answer: stopping the clock to a block that is not in use
Dynamic power is consumed only when nodes switch, and nodes switch only when clocked, so gating the clock to an idle block removes its dynamic power entirely while leaving its state intact. What it does not remove is leakage - the block is still powered. Removing the supply is power gating, which saves the leakage too but loses the state.
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Power gating differs from clock gating in that it also removes
Answer: A
Cutting the supply eliminates leakage as well as switching, which matters most in a deeply sleeping design. The price is that the block loses its state and must be configured again when it returns, which costs both time and energy.
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Leaving an unused peripheral's clock enabled costs
Answer: B
A running timer or converter switches its logic at the clock rate whether or not anything reads it, and several such blocks add up to a substantial fraction of the running current. Enabling clocks only for the peripherals in use is the cheapest saving available.
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An unused input pin left floating on a CMOS device can
Answer: C
Correct answer: draw current by sitting near the switching threshold
A floating CMOS input drifts to whatever the leakage and coupling put it at, and if that is near the threshold both transistors of the input stage conduct, drawing a static current that can be hundreds of microamps - ruinous in a battery design and invisible on a schematic. The remedy is to configure every unused pin as an output, or as an input with the internal pull-up or pull-down enabled.
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An internal pull-up left enabled on a pin driven low externally wastes
Answer: D
A 40 kilohm pull-up on a 3.3 volt rail passes about eighty microamperes continuously, which dwarfs the sleep current of the whole device. Auditing every pin's configuration is part of getting a low power design to its datasheet figure.
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Dynamic voltage and frequency scaling adjusts both because
Answer: A
Logic needs a minimum supply to meet its timing at a given frequency, so relaxing the frequency allows the voltage to come down and the square law then does the work. Scaling frequency alone saves power but very little energy per operation.
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The race-to-idle strategy consists of
Answer: B
Where the sleep mode is very much cheaper than the running mode, finishing quickly and sleeping wins even though the fast running consumes more power. Where leakage dominates and sleep saves little, running slowly at a low voltage wins instead.
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Race-to-idle is the better strategy when
Answer: C
The whole argument rests on sleep being nearly free, so that time spent asleep costs nothing and should be maximised. On a leaky part where sleeping saves little, the quadratic voltage saving from running slowly is worth more.
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A switching regulator is preferred to a linear one when
Answer: D
A linear regulator throws away the voltage difference as heat, so dropping twelve volts to three at half an ampere wastes four and a half watts. A switcher converts instead of dissipating, at the cost of noise, inductors and a higher quiescent current.
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