Match List I with List II :List I (Instruction)List II (Addressing Mode)(a) DJNZ, R3, 100p(1) Implied(b) ADD R4(2) Direct(c) LCALL 2020(3) Register(d) SWAP(4) RelativeCodes : (a) (b) (c) (d)

The correct code is (4) (3) (2) (1).(a) DJNZ R3, label branches by a signed offset from the program counter: relative addressing.(b) ADD with R4 takes its operand from a register: register addressing.(c) LCALL 2020 gives the full 16-bit target address in the instruction, matched here with direct addressing (it is often called long or absolute addressing).(d) SWAP A works on the accumulator named by the opcode itself: implied addressing.Pairs (a), (b) and (d) alone fix the code: only option B gives relative, register and implied in those places.

8051 Programming Questions and Answers

Q: When PUSH PSW instruction is executed, the stack pointer :

The stack pointer decrements by 2.In the 8085, PUSH PSW saves the program status word, the accumulator and the flag register, which is two bytes. The stack grows downward: the stack pointer is decremented and the accumulator stored, then decremented again and the flags stored. Net, SP decreases by 2.Every PUSH in the 8085 moves a register pair, so SP never changes by 1. The stack pointer increments by 2 only on a POP, which removes data from the stack.

Q: MUL A, B instruction of microcontroller 8051 needs :

MUL AB needs 4 machine cycles.The 8051's MUL AB instruction multiplies the unsigned 8-bit numbers in A and B, placing the low byte of the 16-bit product in A and the high byte in B. It is a one-byte instruction, but the multiplication takes 4 machine cycles, the longest of any 8051 instruction; DIV AB also takes 4. At 12 MHz this is 4 µs.Most 8051 instructions take 1 or 2 machine cycles, and none takes 3, so the other options are wrong for MUL.

Q: Which of the following represents indexed addressing ?

Indexed addressing is represented by MOVC A, @ + DPTR (MOVC A, @A+DPTR).In the 8051 the indexed addressing mode forms the address by adding the accumulator to a base register, DPTR or PC. MOVC A,@A+DPTR reads a byte from code memory at that sum, which is how look-up tables are read.AJMP addr is absolute addressing within a 2 K page. SETB 07H (printed 'SET B') sets a bit at a bit address, which is bit (direct) addressing. MOV A,47H copies from internal RAM address 47H, which is direct addressing.

Q: When two BCD numbers are added, the answer is a non-BCD number. To convert it in BCD form the instruction used is :

The instruction is DA A.DA A (decimal adjust accumulator) corrects the result of adding two packed BCD numbers. If a nibble exceeds 9 or produced a carry, it adds 6 to that nibble, giving a valid BCD result. For example 38 + 45 gives 7DH in binary; DA A turns it into 83H, the BCD answer 83.SUBB subtracts with borrow, XCH exchanges the accumulator with a register, and ADD adds in binary; none corrects a sum to BCD.

Q: What is the status of the carry, auxiliary carry and parity flags after executing following instructions ?MOV A,#9CADD A.#64H

After the addition CY = 1, AC = 1 and P = 0; the paper prints the digit 1 as a letter l in this option.The instructions load 9CH into A and add 64H:\[ \begin{aligned} 9C_{H} &= 1001\,1100 \\ 64_{H} &= 0110\,0100 \\ \text{sum} &= 1\;0000\,0000 \end{aligned} \]The result is 100H, so A = 00H and the carry out of bit 7 sets CY = 1. The low nibbles C + 4 = 10H, which carries out of bit 3 and sets AC = 1. The parity flag is set when A holds an odd number of 1s; 00H has none, an even count, so P = 0.Options A and C miss the carry out of bit 7, and option D gets the parity wrong.

When PUSH PSW instruction is executed, the stack pointer :

A.Decrements by 1
B.Increments by 1
C.Increments by 2
D.Decrements by 2

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: D

The stack pointer decrements by 2.

In the 8085, PUSH PSW saves the program status word, the accumulator and the flag register, which is two bytes. The stack grows downward: the stack pointer is decremented and the accumulator stored, then decremented again and the flags stored. Net, SP decreases by 2.

Every PUSH in the 8085 moves a register pair, so SP never changes by 1. The stack pointer increments by 2 only on a POP, which removes data from the stack.

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MUL A, B instruction of microcontroller 8051 needs :

A.4 machine cycles
B.2 machine cycles
C.1 machine cycle
D.3 machine cycles

Exam Year(s)

MH SET - 2019, SET Exam - 2019,

Answer: A

MUL AB needs 4 machine cycles.

The 8051's MUL AB instruction multiplies the unsigned 8-bit numbers in A and B, placing the low byte of the 16-bit product in A and the high byte in B. It is a one-byte instruction, but the multiplication takes 4 machine cycles, the longest of any 8051 instruction; DIV AB also takes 4. At 12 MHz this is 4 µs.

Most 8051 instructions take 1 or 2 machine cycles, and none takes 3, so the other options are wrong for MUL.

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Which of the following represents indexed addressing ?

A.MOVC A, @ + DPTR
B.AJMP addr.
C.SET B 07H
D.MOV A, 47H

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: A

Indexed addressing is represented by MOVC A, @ + DPTR (MOVC A, @A+DPTR).

In the 8051 the indexed addressing mode forms the address by adding the accumulator to a base register, DPTR or PC. MOVC A,@A+DPTR reads a byte from code memory at that sum, which is how look-up tables are read.

AJMP addr is absolute addressing within a 2 K page. SETB 07H (printed 'SET B') sets a bit at a bit address, which is bit (direct) addressing. MOV A,47H copies from internal RAM address 47H, which is direct addressing.

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When two BCD numbers are added, the answer is a non-BCD number. To convert it in BCD form the instruction used is :

A.SUBB A, # data
B.XCH A, Rn
C.ADD A, Rn
D.DA A

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: D

The instruction is DA A.

DA A (decimal adjust accumulator) corrects the result of adding two packed BCD numbers. If a nibble exceeds 9 or produced a carry, it adds 6 to that nibble, giving a valid BCD result. For example 38 + 45 gives 7DH in binary; DA A turns it into 83H, the BCD answer 83.

SUBB subtracts with borrow, XCH exchanges the accumulator with a register, and ADD adds in binary; none corrects a sum to BCD.

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Match List I with List II :

List I (Instruction)	List II (Addressing Mode)
(a) DJNZ, R3, 100p	(1) Implied
(b) ADD R4	(2) Direct
(c) LCALL 2020	(3) Register
(d) SWAP	(4) Relative

Codes : (a) (b) (c) (d)

A.(4) (2) (3) (1)
B.(4) (3) (2) (1)
C.(4) (1) (2) (3)
D.(3) (4) (1) (2)

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: B

The correct code is (4) (3) (2) (1).

(a) DJNZ R3, label branches by a signed offset from the program counter: relative addressing.
(b) ADD with R4 takes its operand from a register: register addressing.
(c) LCALL 2020 gives the full 16-bit target address in the instruction, matched here with direct addressing (it is often called long or absolute addressing).
(d) SWAP A works on the accumulator named by the opcode itself: implied addressing.

Pairs (a), (b) and (d) alone fix the code: only option B gives relative, register and implied in those places.

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What is the status of the carry, auxiliary carry and parity flags after executing following instructions ?

MOV A,#9C
ADD A.#64H

A.CY = 0, AC = 0, P = 0
B.CY = 1, AC = l, P = 0
C.CY = 0, AC = 1, P = 0
D.CY = l, AC = l, P = 1

Exam Year(s)

MH SET - 2024, SET Exam - 2024,

Answer: B

After the addition CY = 1, AC = 1 and P = 0; the paper prints the digit 1 as a letter l in this option.

The instructions load 9CH into A and add 64H:

\[ \begin{aligned} 9C_{H} &= 1001\,1100 \\ 64_{H} &= 0110\,0100 \\ \text{sum} &= 1\;0000\,0000 \end{aligned} \]

The result is 100H, so A = 00H and the carry out of bit 7 sets CY = 1. The low nibbles C + 4 = 10H, which carries out of bit 3 and sets AC = 1. The parity flag is set when A holds an odd number of 1s; 00H has none, an even count, so P = 0.

Options A and C miss the carry out of bit 7, and option D gets the parity wrong.

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