Match List I with List II and select the correct answer using codes given below the list :List IList II(a) S1 = 0, S0 = 0(i) OPCODE FETCH(b) S1 = 0, S0 = 1(ii) READ(c) S1 = 1, S0 = 0(iii) HALT(d) S1 = 1, S0 = 1(iv) WRITE

The correct matching is a-iii, b-iv, c-ii, d-i.The 8085 status signals S1 and S0 identify the type of machine cycle:S1 = 0, S0 = 0: HALT (iii)S1 = 0, S0 = 1: memory or I/O WRITE (iv)S1 = 1, S0 = 0: memory or I/O READ (ii)S1 = 1, S0 = 1: OPCODE FETCH (i)Opcode fetch has both bits set, which rules out the code pairing it with 00, and the code that pairs 01 with READ swaps the read and write cycles.

Microprocessor Architecture Questions and Answers

Q: What is the order decided by a processor or the CPU of a controller to execute an instruction ?

The order is fetch, decode, execute.A processor first fetches the instruction from memory at the address held in the program counter, then decodes it to determine the operation and operands, and only then executes it. The cycle then repeats for the next instruction.An instruction cannot be decoded before it has been fetched, nor executed before it has been decoded, so every other ordering among the options is impossible.

Q: The Program Counter is a :

The Program Counter is a 16-bit up counter with parallel load.In an 8-bit microprocessor such as the 8085, the PC holds the 16-bit address of the next instruction byte. After each byte is fetched it is incremented, so it counts up; and when a jump, call or return occurs, a new address is loaded into it all at once, which requires a parallel load.It is 16 bits wide to address 64 KB of memory, not 8 bits. It never counts down, and it is not a shift register, since addresses are not shifted bit by bit.

Q: The register which acts as an operand and destination of result for arithmetic operations is ........... and the status of result is stored, is ..........

The answer is A, PSW.In the 8085 and similar processors, the accumulator (register A) holds one operand of every arithmetic or logic operation and receives the result. The flags that describe the result (sign, zero, auxiliary carry, parity and carry) are held in the flag register, which together with the accumulator forms the Program Status Word (PSW).B, C and D are general-purpose registers. They can supply the second operand but are not the default destination, and none of them stores the status of the result.

Q: The correct sequence of steps for instruction execution is :

The correct sequence is opcode fetch, decode, execute.The processor first fetches the opcode from the memory location held in the program counter and places it in the instruction register. It then decodes it to work out what operation is required and what operands are needed, and finally executes it, which may involve further memory reads or writes.An instruction cannot be decoded or executed before it has been fetched, so every sequence that starts with decode or execute is impossible.

What is the order decided by a processor or the CPU of a controller to execute an instruction ?

A.Decode, fetch, execute
B.Execute, fetch, decode
C.Fetch, execute, decode
D.Fetch, decode, execute

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: D

The order is fetch, decode, execute.

A processor first fetches the instruction from memory at the address held in the program counter, then decodes it to determine the operation and operands, and only then executes it. The cycle then repeats for the next instruction.

An instruction cannot be decoded before it has been fetched, nor executed before it has been decoded, so every other ordering among the options is impossible.

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Match List I with List II and select the correct answer using codes given below the list :

List I	List II
(a) S1 = 0, S0 = 0	(i) OPCODE FETCH
(b) S1 = 0, S0 = 1	(ii) READ
(c) S1 = 1, S0 = 0	(iii) HALT
(d) S1 = 1, S0 = 1	(iv) WRITE

A.a-i, b-ii, c-iii, d-iv
B.a-iii, b-iv, c-ii, d-i
C.a-ii, b-i, c-iv, d-iii
D.a-iv, b-i, c-ii, d-iii

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: B

The correct matching is a-iii, b-iv, c-ii, d-i.

The 8085 status signals S1 and S0 identify the type of machine cycle:

S1 = 0, S0 = 0: HALT (iii)
S1 = 0, S0 = 1: memory or I/O WRITE (iv)
S1 = 1, S0 = 0: memory or I/O READ (ii)
S1 = 1, S0 = 1: OPCODE FETCH (i)

Opcode fetch has both bits set, which rules out the code pairing it with 00, and the code that pairs 01 with READ swaps the read and write cycles.

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The Program Counter is a :

A.16-bit upcounter with parallel load
B.8-bit up/down counter
C.16-bit down counter with parallel load
D.16-bit Shift Register with parallel load

Exam Year(s)

MH SET - 2021, SET Exam - 2021,

Answer: A

The Program Counter is a 16-bit up counter with parallel load.

In an 8-bit microprocessor such as the 8085, the PC holds the 16-bit address of the next instruction byte. After each byte is fetched it is incremented, so it counts up; and when a jump, call or return occurs, a new address is loaded into it all at once, which requires a parallel load.

It is 16 bits wide to address 64 KB of memory, not 8 bits. It never counts down, and it is not a shift register, since addresses are not shifted bit by bit.

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The register which acts as an operand and destination of result for arithmetic operations is ........... and the status of result is stored, is ..........

A.B, C
B.C, D
C.D, A
D.A, PSW

Exam Year(s)

MH SET - 2021, SET Exam - 2021,

Answer: D

The answer is A, PSW.

In the 8085 and similar processors, the accumulator (register A) holds one operand of every arithmetic or logic operation and receives the result. The flags that describe the result (sign, zero, auxiliary carry, parity and carry) are held in the flag register, which together with the accumulator forms the Program Status Word (PSW).

B, C and D are general-purpose registers. They can supply the second operand but are not the default destination, and none of them stores the status of the result.

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The correct sequence of steps for instruction execution is :

A.Decode, opcode fetch and execute
B.Execute, decode, opcode fetch
C.Opcode fetch, decode, execute
D.Decode, execute, opcode fetch

Exam Year(s)

MH SET - 2021, SET Exam - 2021,

Answer: C

The correct sequence is opcode fetch, decode, execute.

The processor first fetches the opcode from the memory location held in the program counter and places it in the instruction register. It then decodes it to work out what operation is required and what operands are needed, and finally executes it, which may involve further memory reads or writes.

An instruction cannot be decoded or executed before it has been fetched, so every sequence that starts with decode or execute is impossible.

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