Avionics Data Buses Questions and Answers

Answer: C

Correct answer: Only three

The first three are sound. Determinism is a bounded and demonstrable worst-case delivery time; bus loading is the fraction of capacity in use; and a virtual link is a logical unidirectional path to defined receivers.

The fourth confuses determinism with reliability. A deterministic bus can still fail - a severed cable stops it entirely, which is why MIL-STD-1553 and AFDX are both duplicated. What determinism guarantees is when a message arrives if it arrives at all, not that it always will.

Answer: D

Correct answer: Only three

The first three describe the roles correctly: the bus controller directs all traffic, remote terminals respond to its commands, and a bus monitor listens without transmitting.

The fourth is wrong. A bus monitor is passive by definition and cannot take over anything - that passivity is exactly what makes it safe to connect during a test flight. Controller failure is handled by a designated backup bus controller, a separate role with the capability to transmit, not by the monitor.

Answer: A

Correct answer: Cyclic redundancy check

An ARINC 429 word is 32 bits: an eight-bit label, two source destination identifier bits, a data field, a two-bit sign status matrix and a single parity bit. There is no room for a CRC and none is defined.

The parity bit is the whole of the word's error detection, which is weak - it misses every even number of errors. The standard accepts that because a corrupt word is discarded and the parameter is retransmitted within milliseconds, so repetition substitutes for stronger coding.

Answer: B

Correct answer: Any terminal may transmit whenever it has data

That describes a contention bus, and it is the opposite of how MIL-STD-1553 works. No terminal transmits unless the bus controller commands it, which is precisely what makes the traffic deterministic - nothing collides and the worst case follows from the controller's schedule.

The other three are accurate: a bus controller directs all traffic, Manchester encoding is used, and dual redundant buses are provided so that a severed cable does not stop the system.

Answer: C

Correct answer: Digital buses need no error detection

Digital buses need error detection more visibly than analogue wiring did, not less. Noise on an analogue line degrades a value gradually; on a digital bus it corrupts a word outright, which is why every such standard defines parity, a checksum or a CRC.

The other three are the genuine reasons for the change: a large reduction in wiring weight, since many parameters share one medium instead of each having its own pair, and reconfiguration in software rather than by rewiring.

Answer: D

Correct answer: A central polling controller

AFDX has no controller. Each end system transmits on its own virtual links whenever it has data, subject to the bandwidth allocation gap, and the switches police the result - determinism comes from bounding every source in advance rather than from a central authority granting permission.

The other three are all part of the design: virtual links as the logical paths, bandwidth allocation gaps as the rate limits, and dual redundant networks for availability. Central polling is MIL-STD-1553's method, and it is the approach AFDX deliberately replaced.

Answer: A

The other three either detect corruption, survive a path loss or reject data already declared invalid. Raising the loading worsens latency and leaves no margin, which helps integrity not at all. Margin is not integrity.

Answer: B

Correct answer: In the receiver, for ignoring the sign status matrix

The transmitter did its job: it set the sign status matrix to indicate that the data was not to be relied on, which is exactly the mechanism ARINC 429 provides for a source to disclaim its own output.

The receiver failed by reading the data field without checking that flag. Continuing to transmit a flagged word is correct behaviour, not a fault - the alternative, silence, would leave the receiver unable to distinguish a failed source from a severed wire. Parity and wiring are irrelevant, the word having arrived intact.

Answer: C

Two errors leave the parity unchanged, so the word passes every check the standard provides. That blind spot is precisely why later buses carry checksums or cyclic redundancy checks instead. A few extra bits close the gap.

Answer: D

Correct answer: The schedule has little margin left

MIL-STD-1553 traffic runs to a schedule the bus controller holds, and at 75 per cent loading there is little room in it for another function's messages without disturbing the timing of what is already there.

The bus can physically support more terminals - up to 31 - and neither the encoding nor a second controller is at issue. The difficulty is capacity and the worst-case latency that must still be demonstrated afterwards, which is precisely why buses are designed with generous margin at the outset.