Embedded System Architecture Questions and Answers

Answer: C

Being written constantly it must be in read-write memory, and it conventionally grows down from the top of RAM toward the heap and static data. Some very small devices do have a fixed hardware call stack, which limits nesting depth absolutely.

Answer: D

With no memory protection the stack simply grows into whatever is next in RAM and quietly overwrites it, so the symptom appears far from the cause. A guard region filled with a known pattern, or an MPU where one exists, turns it into a reported fault.

Answer: A

Page tables and virtual addressing require a memory management unit, which microcontrollers generally lack: their addresses are physical. Some carry a protection unit, which enforces permissions without translating addresses.

Answer: B

Regions are given read, write and execute permissions and a violation raises a fault, which catches a wild pointer or a stack overflow at the moment it happens. Address translation, and with it demand paging, needs the full management unit.

Answer: C

A core and a DMA controller are both masters, and without arbitration their accesses would collide. The policy the arbiter uses, whether fixed priority or round robin, is what determines the worst-case delay each master can suffer.

Answer: D

Correct answer: deterministic single-cycle access without a cache

Tightly coupled memory sits on its own port beside the core and answers in one cycle every time, with no possibility of a miss. That determinism is what a hard real-time routine or an interrupt handler needs - a cache gives a better average and an unpredictable worst case, and it is the worst case that a deadline is set against.

Answer: A

For a thermostat or a toothbrush the 32-bit part's performance is irrelevant and the pennies and the microamps are not. The 8-bit part loses on precision and reach, and modern 32-bit parts have largely closed the cost gap, which is why the class is shrinking.

Answer: B

Response means the action completed, not merely begun, so the sixty microsecond handler misses a fifty microsecond deadline whatever the latency. Moving the time-critical part to the front of the handler, or into hardware, is the usual remedy.

Answer: C

Correct answer: 16 MB

\[ 2^{24} = 16{,}777{,}216 = 16\ \mathrm{MB}. \] The useful chain to hold is that 2 to the 10 is 1 K, 2 to the 20 is 1 M and 2 to the 30 is 1 G, so 24 lines is \( 2^4 \) times 1 M. The 24 MB offered treats the bit count as a size, which the previous address item warns against.

Answer: D

Each sample occupies two bytes once it is stored in a 16-bit word, so ten thousand samples a second is twenty kilobytes a second. Packing three samples into four bytes would reduce it to fifteen, at the cost of awkward code.