Embedded System Architecture Questions and Answers

Answer: A

Correct answer: 1 and 3 only are correct

Statements 1 and 3 are correct: latency includes saving the context as well as recognising the interrupt, and a peripheral flag left uncleared re-asserts the request the moment the handler returns, so it runs again immediately. Statement 2 contradicts the definition - a non-maskable interrupt is precisely one that cannot be disabled in software, which is why it is reserved for events such as power failure.

Answer: B

The shared bus of a von Neumann machine forces the fetch and the data access into separate cycles, and removing that constraint is exactly where the extra throughput comes from. The cost is more silicon and, on an external bus, more pins.

Answer: C

The qualifier is needed because the hardware can change the location behind the compiler's back, which is the opposite of being read-only. Many peripheral registers are writable and some are write-only, and all of them need the qualifier.

Answer: D

Dynamic power is proportional to the capacitance, the square of the supply and the frequency, so frequency alone enters linearly. Reducing the supply as well is what gives the quadratic saving, which is why voltage scaling accompanies frequency scaling.

Answer: A

Since power goes as the square of the supply and only linearly with frequency, doing the same work more slowly at a lower voltage wins. Widening the datapath restores the throughput lost to the lower clock, which is the standard parallelism-for-voltage trade.

Answer: B

Twelve cycles at 48 MHz is 12 divided by 48 million, that is a quarter of a microsecond. Whether that is acceptable depends entirely on the deadline: it is generous for a keypad and far too slow for a switching converter's current loop.

Answer: C

Correct answer: the figure is impossible, one cycle alone being 62.5 ns

At 16 MHz a single clock cycle is \[ \frac{1}{16\times10^{6}} = 62.5\ \mathrm{ns}, \] and taking an interrupt costs at least a handful of cycles for recognition, vector fetch and context save. A latency of 2 ns is a small fraction of one cycle and therefore impossible on this part - the figure has probably been quoted in cycles and mislabelled as nanoseconds.

Answer: D

Correct answer: any memory instruction and any pointer in C can reach a peripheral

With peripherals in the ordinary address space, no special instructions are needed: a load or store reaches a register, and in C a pointer to a volatile struct describes a whole peripheral. Port-mapped I/O requires dedicated IN and OUT instructions that most modern RISC cores do not have and that C cannot express portably. The cost is address space, which is ample on a 32-bit core.

Answer: A

Wrong load capacitance or excessive drive gives an oscillator that starts unreliably or runs at the wrong frequency, and layout matters as much as component value. The other three would fail identically on either clock source.

Answer: B

Fewer than four thousand writes over the life is nothing against the hundred thousand cycles such parts endure, so ordinary non-volatile memory suffices. SRAM loses the data at power off and mask ROM cannot be written at all.