A phase locked loop in a microcontroller's clock tree is used to
Answer: A
A cheap 8 or 16 MHz crystal can then drive a core at 168 MHz, which avoids both an expensive high frequency crystal and the radiated emissions of a fast external clock. Dividers handle the peripheral clocks and a separate monitor watches for crystal failure.
Please log in or register to report this question.
An external crystal is preferred to the internal RC oscillator when the application needs
Answer: B
An internal RC oscillator is typically within a per cent or two over temperature, which is enough for a delay loop and not enough for a UART at high speed. The crystal costs two pins, two capacitors, some board area and a slower start-up.
Please log in or register to report this question.
Instruction pipelining raises throughput by
Answer: C
Each instruction still takes the same number of stages, but one completes every cycle once the pipeline is full, so the rate rises without the latency of any single instruction falling. A taken branch empties the pipeline, which is why branch prediction matters.
Please log in or register to report this question.
A taken branch on a pipelined processor costs extra cycles because
Answer: D
Fetching proceeds along the sequential path, so a taken branch invalidates whatever has been brought in behind it and the pipeline refills from the target. This branch penalty is why tight loops are sometimes unrolled and why prediction hardware exists.
Please log in or register to report this question.
A cache improves average access time because programs exhibit
Answer: A
Recently used data is likely to be used again and neighbouring addresses are likely to follow, so a small fast memory holding the working set catches most accesses. A program with no locality gains nothing from a cache and may be slowed by it.
Please log in or register to report this question.
Caches are often avoided or lockable in hard real time embedded systems because
Answer: B
Average speed is not the figure a deadline is judged against; the worst case is, and a cache makes it depend on history. Locking a critical routine into cache, or using a tightly coupled memory instead, restores predictability.
Please log in or register to report this question.
A little-endian machine stores the least significant byte of a multi-byte value at
Answer: C
Big-endian does the reverse, putting the most significant byte first, which reads naturally in a memory dump. Neither is better, but a value written by one and read by the other comes back byte-reversed, which is why network protocols specify an order.
Please log in or register to report this question.
A little-endian 32-bit machine executes the following.
uint32_t v = 0x12345678; uint8_t *p = (uint8_t *)&v;
The value of p[0] is
Answer: D
The least significant byte occupies the lowest address on a little-endian machine, so the first byte of the object is 0x78. On a big-endian machine the same code would yield 0x12, which is why casting a pointer this way is not portable.
Please log in or register to report this question.
What is the value of x after these three lines run?
uint8_t x = 0xF0; x = x >> 2; x |= 0x03;
Answer: A
Shifting 0xF0 right by two gives 0x3C, and setting the two low bits with an inclusive or gives 0x3F. Working in binary rather than hex makes such manipulations far less error-prone: 1111 0000 becomes 0011 1100 and then 0011 1111.
Please log in or register to report this question.
A port register is manipulated as follows.
uint8_t p = 0x00; p |= (1 << 3); p &= ~(1 << 1);
The final value of p is
Answer: B
Correct answer: 0x08
\( 1 \ll 3 \) is 0x08, so the OR sets bit 3 and gives 0x08. \( \sim(1 \ll 1) \) is 0xFD, and ANDing with it clears bit 1 - which was already clear, so nothing changes. The final value is 0x08. This set-then-clear idiom is the standard way of touching one bit of a port without disturbing the others.
Please log in or register to report this question.
