Embedded System Architecture Questions and Answers

Answer: A

Any instruction that can touch memory can then touch a peripheral, which is why a memory-mapped device is so convenient in C. The cost is address space consumed and the need to mark those addresses volatile so the compiler does not optimise the accesses away.

Answer: B

The x86 family's IN and OUT instructions are the familiar example, and the separate space leaves the whole memory map for memory. Almost every modern embedded core is memory-mapped instead, which is simpler to program and to describe in a header file.

Answer: C

Without it the compiler is entitled to assume nothing else changes the location and may read it once, or not at all. The qualifier forbids that optimisation; it says nothing about ordering between separate accesses, which needs a barrier.

Answer: D

On accepting an interrupt the hardware indexes the table by source and jumps to the address found there, which is why the table must be placed where the core expects it. Priorities live in the interrupt controller and pending flags in the peripherals.

Answer: A

It comprises the time to finish or abandon the current instruction, to save context and to fetch the vector, and a core intended for real time work quotes it as a fixed number of cycles. What the handler then does is its execution time, not its latency.

Answer: B

A longer handler lengthens the time before the *next* interrupt is served but has no effect on the latency of this one, and it makes matters worse for everything else. The other three all attack a real component of the delay.

Answer: C

It is reserved for conditions that must be handled whatever the software is doing, typically a supply failure or a memory error. Because it cannot be blocked, its handler must be written to run safely at any moment, which is a strong constraint.

Answer: D

Correct answer: a higher priority interrupt may interrupt a handler already running

Nesting allows a handler to be pre-empted by a source of higher priority, so an urgent event is not held up behind a slower one. It is what keeps worst-case latency bounded for the highest-priority source, and its cost is stack depth - each nested level saves another context, so the stack must be sized for the deepest possible nesting.

Answer: A

Most peripherals latch a flag that the handler must clear explicitly, and an uncleared flag re-asserts the request the moment the handler returns. A wrong vector address gives a crash rather than a loop, and an undersized stack gives corruption.

Answer: B

The instruction in progress is disposed of first, then the return state is pushed, then the priority mask is raised so the handler is not immediately displaced by an equal source, and only then does control transfer. Cores differ in detail but not in this order.