CMOS Fabrication Process Questions and Answers

Answer: A

Chemical composition is obtained with EDAX.

In energy-dispersive X-ray analysis, the electron beam of an electron microscope knocks inner-shell electrons out of the atoms in the sample. As the atoms relax they emit X-rays whose energies are characteristic of each element, so the spectrum shows which elements are present and in what proportion.

TEM gives images and diffraction patterns of the internal structure, SEM alone images surface topography, and XRD gives crystal structure and phase. None of them on its own measures elemental composition.

Answer: D

The key gives Fabrication of p-MOS transistor requires few additional steps compared to n-MOS transistor.

In the common n-well CMOS process the starting wafer is p-type, so the nMOS transistors are built directly in the substrate. The pMOS transistors need an n-type region to sit in, which means extra steps: an n-well mask, the n-well implant and drive-in, and a separate p+ source/drain implant with its own mask. So the pMOS device is the one that costs additional processing.

The first option reverses this. The second is wrong because the two devices need different well and implant steps, and the third, while loosely true, does not identify the specific point the question tests.

Answer: A

As die size shrinks, the complexity of making photomasks increases.

Shrinking a die means shrinking its features. Smaller lines and spaces have to be written on the mask with tighter dimensional tolerance and tighter alignment between layers, and once features fall below the wavelength of the exposure light, the mask also needs optical proximity correction, phase-shift features and sub-resolution assist features to print correctly. Each step adds to mask writing time, inspection and cost.

The complexity therefore cannot decrease or stay the same, and the trend is well established, so it is not something that 'cannot be determined'.

Answer: B

The key gives Boats.

In furnace-type processing the wafers are stood or laid in a carrier called a boat (quartz, or graphite coated with silicon carbide in an epitaxial reactor, where the heated carrier is also called the susceptor) and pushed into the reaction chamber. The gas carrying the silicon source, for example silicon tetrachloride or silane in hydrogen, flows over the heated wafers and deposits a single-crystal silicon layer.

An ingot is the large single crystal grown by the Czochralski process, from which wafers are sliced, so wafers are not placed in it. A crucible holds molten silicon during crystal growth, not wafers. 'Cup' is not the term used for a wafer carrier.

Answer: B

The masking chemical is silicon nitride.

In the LOCOS (local oxidation of silicon) process, a patterned layer of silicon nitride, Si₃N₄, covers the active areas where transistors will be built. Oxygen and water vapour diffuse through nitride extremely slowly, so the field oxide grows only in the exposed regions, isolating neighbouring devices.

Silver nitride is not used in silicon processing. Hydrofluoric acid etches silicon dioxide; it removes oxide rather than masking against its growth. Polysilicon is used for gates and as a buffer layer in some LOCOS variants, but it oxidises readily and is not the mask itself.

Answer: B

Single-crystal silicon layers are obtained by epitaxial growth.

Epitaxy deposits a thin layer of silicon on a single-crystal wafer so that the new layer continues the crystal structure of the substrate. It is used, for example, to grow a lightly doped layer over a heavily doped substrate or buried layer, as in bipolar ICs, with doping controlled independently of the substrate.

Oxidation grows amorphous silicon dioxide, not crystal silicon. Photolithography transfers patterns. Wafer preparation produces the starting substrate; it does not build up single-crystal layers during IC fabrication, which is what the question asks.

Answer: A

The key takes both statements as correct and the reason as the explanation, the first option. Mobile positive ions, such as sodium, trapped in the oxide between the gate and the substrate, add a positive charge that acts like a positive gate voltage on the channel.

In a p-channel enhancement device, which needs a negative gate voltage to turn on, this shifts the threshold so that the device can turn on prematurely, and the reason describes this contamination. So the reason explains the assertion, and the options that deny this are not the keyed answer.

Answer: B

After the wafer is coated with photoresist, it is exposed to UV radiation through a mask (2), the exposed or unexposed resist is dissolved in the developer (4), the oxide or metal not protected by the resist is etched (1), and the remaining resist is stripped (3). The order is 2, 4, 1, 3. The mask exposes the resist to UV light first, the developer then removes the soluble part of it to open windows, etching removes the exposed oxide through these windows, and only then is the leftover resist stripped, because the resist is needed as the protective layer during etching. The answer is 2, 4, 1, 3.

Answer: B

The sequence of IC fabrication is crystal growth, epitaxial growth, photo etching, diffusion and vacuum evaporation of aluminium for the interconnections, which is 1, 2, 3, 4, 5. Metallisation has to come last because the diffusions would damage the aluminium at their high temperature. The other orders put evaporation or diffusion in the wrong place.

Answer: C

The correct sequence is 3, 4, 2, 1: buried layer formation, epitaxial layer growth, base diffusion, emitter diffusion. The n+ buried layer is made first on the p substrate, the n epitaxial layer is grown over it, then the p base is diffused into that layer, and last the n+ emitter is diffused into the base.

The emitter must go after the base because it lies inside it. The buried layer must go before the epi-layer because it lies beneath it. Every other order breaks one of these rules.