Basic Computer Organisation Questions and Answers

Q: If a byte is used as a storage unit, number 5 and character 5 in assembly language are stored as :

They are stored as 00000101B and 00110101B.The number 5 is stored in pure binary: \(5 = 101_2\), which in a byte is 00000101. The character '5' is stored as its ASCII code, 35H = 53 decimal, which is 00110101 in binary.Option C's 00000011 is 3, not 5, and option B's 01110101C is not a valid binary byte. So only option A is right, and 'None of the above' is wrong.

Q: A t-state is measured from the falling edge of one clock pulse to the falling edge of the next clock pulse. Fetch cycle and the execution cycle take how many of the following t-states ?

The answer is 4 and 3.Taking the 8085 as the standard example, the opcode fetch machine cycle takes four T-states: three to place the address, read the opcode from memory and latch it, and a fourth in which the processor decodes it. A memory read or write machine cycle in the execution phase takes three T-states, since no decoding is needed.So an instruction such as MVI A, data takes 4 T-states to fetch the opcode and 3 more to read the data byte. The option '3 and 4' reverses the two, and 2 and 1, or 2 and 3, are too few for either cycle.

Q: The following Truth Table represents which Logical Micro-operation ?ABF000011101110

The table is the exclusive OR, \(F \leftarrow A \oplus B\).F is 1 exactly when A and B differ (01 and 10) and 0 when they are equal (00 and 11). That is the XOR micro-operation.AND would give 1 only for 11. NAND would give 1 for 00, 01 and 10. XNOR, the complement of XOR, would give 1 for 00 and 11, the opposite of the table.

Q: What is the interpretation of "R1 ← R2" instruction in Register Transfer Language ?

R1 ← R2 means load the content of R2 into R1.In register transfer language the arrow shows a transfer: the contents of the source register on the right are copied into the destination register on the left. The transfer is non-destructive, so R2 keeps its value.Addition would be written R1 ← R1 + R2. Nothing in the statement clears R2, so the two options that delete its contents describe a different operation.

Q: The "instruction decode" phase in CPU's instruction cycle is responsible to ................. .

Instruction decode determines the opcode and operands of the instruction.After the fetch phase has brought the instruction into the instruction register, the control unit decodes it: it interprets the opcode to find which operation is required and works out the operands and addressing mode, so the right control signals can be generated.Loading the instruction into the CPU is the fetch phase. The instruction is already in machine code, so nothing is translated at this stage; translation from source to machine code is done earlier by a compiler or assembler. Carrying out the operation is the execute phase.

Q: Identify an appropriate operation sequence with respect to execution of a machine level language instruction.

The correct sequence is load instruction address, get the instruction, get effective address of operands, execute the opcode.The instruction cycle starts by placing the program counter's address on the bus, then fetches the instruction from memory. Once it is decoded, the CPU computes the effective addresses of its operands (fetching them if they are in memory), and only then executes the operation.The other sequences are impossible: the CPU cannot work out operand addresses before it has fetched the instruction that names them, and it cannot execute before it has its operands.

Q: The ADD micro-operation in the register transfer R1 ← R2 + R3 takes place in which of the following ?

The addition takes place in the ALU execution phase.The register transfer R1 ← R2 + R3 means: read R2 and R3, add them, and store the sum in R1. The values are already in registers, so no memory access is needed. They are placed on the ALU's inputs, the ALU performs the ADD micro-operation during the execute phase, and the result is written into R1.The MAR loading phase concerns placing a memory address in the memory address register for a read or write, which this register-to-register operation does not need. The operand fetch phase only brings the operands to the ALU; the addition itself is execution. So 'None of these' is wrong.

Q: Which architecture uses a single memory for both instructions and data ?

The architecture is Von Neumann.In the Von Neumann architecture, programs and data are stored in the same memory and travel over the same bus. This makes the design simple and flexible, but the processor cannot fetch an instruction and data at the same moment, a limit known as the Von Neumann bottleneck.The Harvard architecture uses separate memories and buses for instructions and data, common in microcontrollers and DSPs. Superscalar describes a processor that issues several instructions per cycle, and RISC is an instruction-set philosophy; neither is defined by how memory is organised.

Q: In the 8085 microprocessor, the flag register consists of how many flags ?

The 8085 flag register has 5 flags.The five flags are Sign (S), Zero (Z), Auxiliary Carry (AC), Parity (P) and Carry (CY). They occupy five of the register's eight bits; the other three are unused.So 2, 4 and 6 are wrong counts.The flags are set or cleared by the ALU after arithmetic and logic operations and are tested by conditional jumps such as JZ and JC.

Q: In the 8086 microprocessor, the bus width is

The 8086 has a 16 bits data bus.The 8086 is a 16-bit microprocessor: its data bus and internal registers are 16 bits wide. Its address bus is 20 bits wide, which lets it address 1 MB of memory.8 bits is the data bus of the 8085 (and of the 8088 variant), while 32 and 64 bits belong to later processors such as the 80386 and modern x86-64 chips.The 8086's 16-bit data bus is multiplexed with the lower part of its address bus on the same pins.

If a byte is used as a storage unit, number 5 and character 5 in assembly language are stored as :

A.00000101B and 00110101B
B.01110101C and 00110101B
C.00000011B and 00000101B
D.None of the above

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: A

They are stored as 00000101B and 00110101B.

The number 5 is stored in pure binary: \(5 = 101_2\), which in a byte is 00000101. The character '5' is stored as its ASCII code, 35H = 53 decimal, which is 00110101 in binary.

Option C's 00000011 is 3, not 5, and option B's 01110101C is not a valid binary byte. So only option A is right, and 'None of the above' is wrong.

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A t-state is measured from the falling edge of one clock pulse to the falling edge of the next clock pulse. Fetch cycle and the execution cycle take how many of the following t-states ?

A.2 and 1
B.3 and 4
C.4 and 3
D.2 and 3

Exam Year(s)

MH SET - 2021, SET Exam - 2021,

Answer: C

The answer is 4 and 3.

Taking the 8085 as the standard example, the opcode fetch machine cycle takes four T-states: three to place the address, read the opcode from memory and latch it, and a fourth in which the processor decodes it. A memory read or write machine cycle in the execution phase takes three T-states, since no decoding is needed.

So an instruction such as MVI A, data takes 4 T-states to fetch the opcode and 3 more to read the data byte. The option '3 and 4' reverses the two, and 2 and 1, or 2 and 3, are too few for either cycle.

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The following Truth Table represents which Logical Micro-operation ?

A	B	F
0	0	0
0	1	1
1	0	1
1	1	0

A.\(F \leftarrow A \wedge B\)
B.\(F \leftarrow \overline{A \wedge B}\)
C.\(F \leftarrow A \oplus B\)
D.\(F \leftarrow \overline{A \oplus B}\)

Exam Year(s)

MH SET - 2024, SET Exam - 2024,

Answer: C

The table is the exclusive OR, \(F \leftarrow A \oplus B\).

F is 1 exactly when A and B differ (01 and 10) and 0 when they are equal (00 and 11). That is the XOR micro-operation.

AND would give 1 only for 11. NAND would give 1 for 00, 01 and 10. XNOR, the complement of XOR, would give 1 for 00 and 11, the opposite of the table.

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What is the interpretation of "R1 ← R2" instruction in Register Transfer Language ?

A.Load the content of R2 into R1
B.Add the content of R2 into R1
C.Load the content of R2 into R1 and then delete the contents of R2
D.Add the content of R2 into R1 and then delete the contents of R2

Exam Year(s)

MH SET - 2025, SET Exam - 2025,

Answer: A

R1 ← R2 means load the content of R2 into R1.

In register transfer language the arrow shows a transfer: the contents of the source register on the right are copied into the destination register on the left. The transfer is non-destructive, so R2 keeps its value.

Addition would be written R1 ← R1 + R2. Nothing in the statement clears R2, so the two options that delete its contents describe a different operation.

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The "instruction decode" phase in CPU's instruction cycle is responsible to ................. .

A.load the instruction into CPU
B.translate the instruction into machine language code
C.determine the opcode and operands of the instruction
D.execute the operation specified by the instruction

Exam Year(s)

MH SET - 2025, SET Exam - 2025,

Answer: C

Instruction decode determines the opcode and operands of the instruction.

After the fetch phase has brought the instruction into the instruction register, the control unit decodes it: it interprets the opcode to find which operation is required and works out the operands and addressing mode, so the right control signals can be generated.

Loading the instruction into the CPU is the fetch phase. The instruction is already in machine code, so nothing is translated at this stage; translation from source to machine code is done earlier by a compiler or assembler. Carrying out the operation is the execute phase.

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Identify an appropriate operation sequence with respect to execution of a machine level language instruction.

A.Load instruction address-get the instruction-execute the opcode-get effective address of operands
B.Load instruction address-get effective address of operands-get the instruction-execute the opcode
C.Load instruction address-get the instruction-get effective address of operands-execute the opcode
D.Load instruction address-get effective address of operands-execute the opcode-get the instruction

Exam Year(s)

MH SET - 2025, SET Exam - 2025,

Answer: C

The correct sequence is load instruction address, get the instruction, get effective address of operands, execute the opcode.

The instruction cycle starts by placing the program counter's address on the bus, then fetches the instruction from memory. Once it is decoded, the CPU computes the effective addresses of its operands (fetching them if they are in memory), and only then executes the operation.

The other sequences are impossible: the CPU cannot work out operand addresses before it has fetched the instruction that names them, and it cannot execute before it has its operands.

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The ADD micro-operation in the register transfer R1 ← R2 + R3 takes place in which of the following ?

A.MAR loading phase
B.ALU execution phase
C.Operand fetch phase
D.None of these

Exam Year(s)

Tripura Public Service Commission - 2026,

Answer: B

The addition takes place in the ALU execution phase.

The register transfer R1 ← R2 + R3 means: read R2 and R3, add them, and store the sum in R1. The values are already in registers, so no memory access is needed. They are placed on the ALU's inputs, the ALU performs the ADD micro-operation during the execute phase, and the result is written into R1.

The MAR loading phase concerns placing a memory address in the memory address register for a read or write, which this register-to-register operation does not need. The operand fetch phase only brings the operands to the ALU; the addition itself is execution. So 'None of these' is wrong.

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Which architecture uses a single memory for both instructions and data ?

A.Harvard
B.Von Neumann
C.Superscalar
D.RISC

Exam Year(s)

Tripura Public Service Commission - 2026,

Answer: B

The architecture is Von Neumann.

In the Von Neumann architecture, programs and data are stored in the same memory and travel over the same bus. This makes the design simple and flexible, but the processor cannot fetch an instruction and data at the same moment, a limit known as the Von Neumann bottleneck.

The Harvard architecture uses separate memories and buses for instructions and data, common in microcontrollers and DSPs. Superscalar describes a processor that issues several instructions per cycle, and RISC is an instruction-set philosophy; neither is defined by how memory is organised.

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In the 8085 microprocessor, the flag register consists of how many flags ?

Exam Year(s)

Tripura Public Service Commission - 2025,

Answer: C

The 8085 flag register has 5 flags.

The five flags are Sign (S), Zero (Z), Auxiliary Carry (AC), Parity (P) and Carry (CY). They occupy five of the register's eight bits; the other three are unused.

So 2, 4 and 6 are wrong counts.

The flags are set or cleared by the ALU after arithmetic and logic operations and are tested by conditional jumps such as JZ and JC.

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10.

In the 8086 microprocessor, the bus width is

A.8 bits
B.16 bits
C.32 bits
D.64 bits

Exam Year(s)

Tripura Public Service Commission - 2025,

Answer: B

The 8086 has a 16 bits data bus.

The 8086 is a 16-bit microprocessor: its data bus and internal registers are 16 bits wide. Its address bus is 20 bits wide, which lets it address 1 MB of memory.

8 bits is the data bus of the 8085 (and of the 8088 variant), while 32 and 64 bits belong to later processors such as the 80386 and modern x86-64 chips.

The 8086's 16-bit data bus is multiplexed with the lower part of its address bus on the same pins.

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