Cache Memory Design Questions and Answers

Q: The access time of cache memory is 10 ns and main memory is 100 ns. If the hit ratio is 0.9, what is the average memory access time ?

The average memory access time is 19 ns.Taking cache and main memory as accessed in parallel, a hit costs the cache time and a miss costs the main memory time:\[ \begin{aligned} T &= h\,t_c + (1-h)\,t_m \\ &= 0.9 \times 10 + 0.1 \times 100 \\ &= 9 + 10 = 19\ \text{ns} \end{aligned} \]If the cache is checked first and a miss then goes to main memory, a miss costs 110 ns and the average is 20 ns, which is not offered, so the paper uses the simpler model. 55 ns is the plain mean of 10 and 100, ignoring the hit ratio, and 90 ns is \(0.9 \times 100\), applying the hit ratio to the wrong memory.

Q: A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The number of bits in the tag field of an address is

The tag field has 16 bits.Work out the number of sets and the block offset:\[ \begin{aligned} \text{blocks} &= 256\text{K} / 32 = 8192 \\ \text{sets} &= 8192 / 4 = 2048 = 2^{11} \\ \text{offset} &= \log_{2} 32 = 5 \\ \text{tag} &= 32 - 11 - 5 = 16 \end{aligned} \]The valid, modified and replacement bits are stored with the tag in the directory, but they are not part of the address, so they do not change the tag length. 27 would ignore the set index, and 11 is the index itself.

Q: How many 32K×1 RAM chips are needed to provide a memory capacity of 256K-bytes ?

The number of chips is 64.The memory needed is 256K bytes, that is 256K words of 8 bits. Each chip holds 32K words of 1 bit, so we need 8 chips side by side for the 8-bit width, and 256K / 32K = 8 such rows for the depth:\[ \begin{aligned} \frac{256\text{K}}{32\text{K}} \times \frac{8}{1} &= 8 \times 8 \\ &= 64 \end{aligned} \]8 counts only the rows or only the width, 32 is half the answer, and 128 doubles it.

11.

The access time of cache memory is 10 ns and main memory is 100 ns. If the hit ratio is 0.9, what is the average memory access time ?

A.19 ns
B.28 ns
C.55 ns
D.90 ns

Exam Year(s)

Tripura Public Service Commission - 2026,

Answer: A

The average memory access time is 19 ns.

Taking cache and main memory as accessed in parallel, a hit costs the cache time and a miss costs the main memory time:

\[ \begin{aligned} T &= h\,t_c + (1-h)\,t_m \\ &= 0.9 \times 10 + 0.1 \times 100 \\ &= 9 + 10 = 19\ \text{ns} \end{aligned} \]

If the cache is checked first and a miss then goes to main memory, a miss costs 110 ns and the average is 20 ns, which is not offered, so the paper uses the simpler model. 55 ns is the plain mean of 10 and 100, ignoring the hit ratio, and 90 ns is \(0.9 \times 100\), applying the hit ratio to the wrong memory.

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12.

A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The number of bits in the tag field of an address is

A.11
B.14
C.16
D.27

Exam Year(s)

Tripura Public Service Commission - 2025,

Answer: C

The tag field has 16 bits.

Work out the number of sets and the block offset:

\[ \begin{aligned} \text{blocks} &= 256\text{K} / 32 = 8192 \\ \text{sets} &= 8192 / 4 = 2048 = 2^{11} \\ \text{offset} &= \log_{2} 32 = 5 \\ \text{tag} &= 32 - 11 - 5 = 16 \end{aligned} \]

The valid, modified and replacement bits are stored with the tag in the directory, but they are not part of the address, so they do not change the tag length. 27 would ignore the set index, and 11 is the index itself.

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13.

How many 32K×1 RAM chips are needed to provide a memory capacity of 256K-bytes ?

A.8
B.32
C.64
D.128

Exam Year(s)

Tripura Public Service Commission - 2025,

Answer: C

The number of chips is 64.

The memory needed is 256K bytes, that is 256K words of 8 bits. Each chip holds 32K words of 1 bit, so we need 8 chips side by side for the 8-bit width, and 256K / 32K = 8 such rows for the depth:

\[ \begin{aligned} \frac{256\text{K}}{32\text{K}} \times \frac{8}{1} &= 8 \times 8 \\ &= 64 \end{aligned} \]

8 counts only the rows or only the width, 32 is half the answer, and 128 doubles it.

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