Instruction Set Architecture Questions and Answers

Q: A processor has 64 general-purpose registers and 50 distinct instruction types. An instruction is encoded in 32-bits. What is the maximum number of bits that can be used to store the immediate operand for the given instruction?ADD R1, #25 // R1 = R1 + 25

At most 20 bits are left for the immediate operand.The instruction ADD R1, #25 has three fields: the opcode, one register and the immediate value.\[ \begin{aligned} \text{opcode} &= \lceil \log_{2} 50 \rceil = 6\ \text{bits} \\ \text{register} &= \log_{2} 64 = 6\ \text{bits} \\ \text{immediate} &= 32 - 6 - 6 = 20\ \text{bits} \end{aligned} \]Five bits would allow only 32 instruction types, so six are needed for 50. 16 bits would set aside 4 more bits than the instruction's fields need, while 22 and 24 bits would leave only 10 or 8 bits for the opcode and register together, too few to encode 50 instruction types and 64 registers.

Q: Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the first operand of any instruction is the destination operand.Which one of the following sequences of instructions corresponds to the high-level language statement Z = X + Y ?Note: X, Y, and Z are memory operands. R0, R1, and R2 are registers.

The correct sequence is LOAD R0, X / LOAD R1, Y / ADD R2, R0, R1 / STORE Z, R2.In a load-store architecture only LOAD and STORE may access memory; arithmetic instructions work on registers only. So both operands must first be loaded into registers, added register to register, and the result stored back to Z.ADD Z, X, Y uses three memory operands. 'LOAD R0, X / ADD Z, R0, Y' still has the ADD reading Y from memory and writing Z to memory. 'ADD R0, X, Y / STORE Z, R0' has the ADD reading X and Y from memory. Each breaks the load-store rule.

Q: Which of the following is/are part of an Instruction Set Architecture of a processor?

Only the total number of registers is part of the Instruction Set Architecture.The ISA is the interface between hardware and software: everything a machine-language programmer or compiler must know, such as the instructions, addressing modes, data types and the programmer-visible registers. Instructions name registers in their operand fields, so the number of registers is fixed by the ISA.The size of the cache, the number of cache levels and the clock frequency are properties of a particular implementation (the microarchitecture). Two processors with the same ISA can differ in all three and still run the same programs unchanged, which is why none of them is part of the ISA.

Q: Consider a processor that has 16 general purpose registers and it uses 2-byte instruction format for all its instructions. Variable-sized opcodes are permitted. There are three different types of instructions; M-type, R-type, and C-type. Each M-type instruction has 2 register operands and a 6-bit immediate operand. Each R-type instruction has 3 register operands. Each C-type instruction has a register operand and a 6-bit offset value. If there are 2 unique M-type opcodes and 7 unique R-type opcodes, which one of the following options gives the maximum number of unique opcodes possible for C-type instructions?

The maximum number of C-type opcodes is 4.Each instruction is 16 bits, and with 16 registers a register field needs 4 bits. The bits left for the opcode in each type:M-type: 2 registers + 6-bit immediate = 14 bits, leaving a 2-bit opcode;R-type: 3 registers = 12 bits, leaving 4 bits;C-type: 1 register + 6-bit offset = 10 bits, leaving 6 bits.With an expanding opcode, the 2-bit field gives 4 patterns. M-type uses 2; the other 2 become prefixes for longer opcodes. Extending each by 2 bits gives 2 × 4 = 8 four-bit patterns. R-type uses 7, leaving 1 as a prefix. Extending it by the last 2 bits gives 4 six-bit patterns, so C-type can have at most 4 opcodes.64 would be the count if the whole 6-bit field were free, and 16 or 8 forget that the M-type and R-type opcodes have already used up most of the prefixes.

Q: Consider the following processor design characteristics.I. Register-to-register arithmetic operations onlyII. Fixed-length instruction formatIII. Hardwired control unitWhich of the characteristics above are used in the design of a RISC processor?

All three are RISC characteristics, so the answer is I, II and III.A RISC processor is a load-store machine: arithmetic works only on registers, and memory is reached only by load and store instructions (I). Its instructions have a fixed length, usually one word, which makes fetching and decoding simple and pipelining easy (II). With a small set of simple instructions, the control unit can be hardwired rather than microprogrammed, which is faster (III).Each two-item option leaves out one of these, so none of them is complete. Variable-length instructions, memory operands in arithmetic and microprogrammed control are the CISC features they contrast with.

Q: Consider the given C-code and its corresponding assembly code, with a few operands U1-U4 being unknown. Some useful information as well as the semantics of each unique assembly instruction is annotated as inline comments in the code. The memory is byte-addressable.//C-codeint a[10], b[10], i;// int is 32-bitfor (i=0; i\(\lt\)10;i++)a[i] = b[i] * 8;;assembly-code (; indicates comments);r1-r5 are 32-bit integer registers;initialize r1=0, r2=10;initialize r3, r4 with base address of a, bL01: jeq r1, r2, end ;if(r1==r2) goto endL02: lw r5, 0(r4) ;r5 \(\lt\)- Memory[r4+0]L03: shl r5, r5, U1 ;r5 \(\lt\)- r5 \(\lt\lt\) U1L04: sw r5, 0(r3) ;Memory[r3+0] \(\lt\)- r5L05: add r3, r3, U2 ;r3 \(\lt\)- r3+U2L06: add r4, r4, U3L07: add r1, r1, 1L08: jmp U4 ;goto U4L09: endWhich one of the following options is a CORRECT replacement for operands in the position (U1, U2, U3, U4) in the above assembly code?

The operands are (3, 4, 4, L01).U1: multiplying by 8 is a left shift by 3 bits, since \(8 = 2^{3}\). A shift of 8 would multiply by 256.U2 and U3: an int is 32 bits, 4 bytes, and memory is byte-addressable, so the pointers r3 (into a) and r4 (into b) must each advance by 4 to reach the next element.U4: after r1 is incremented, the loop must test r1 == r2 again before the next iteration, so it jumps back to L01. Jumping to L02 skips the test and never leaves the loop.(8, 4, 1, L02) gets the shift, the b pointer and the jump wrong; (8, 1, 1, L02) also steps the pointers by a single byte; and (3, 1, 1, L01) has the right shift and jump but moves only one byte per element, reading and writing overlapping parts of the integers.

Which of the given options best describes the truthfulness of the following statements?

i) A compiler translates the entire source code line by line.
ii) Computer architecture refers to those attributes of a system visible to a programmer.
iii) The Reduced Instruction Set Architecture (RISC) computer organisation reduces the cycles per instruction at the cost of the number of instructions per program to increase the CPU performance.
iv) All the arithmetic and logical processing is performed by the Arithmetic Logic Unit under the supervision of a control unit.

A.i-True, ii-True, iii-True, iv-True
B.i-False, ii-True, iii-True, iv-True
C.i-True, ii-False, iii-True, iv-True
D.i-False, ii-False, iii-True, iv-False

Exam Year(s)

DSSSB TGT - 2023,

Answer: B

Statement i is false and statements ii, iii and iv are true. A compiler translates the whole source program at once into machine code, and it is an interpreter that works line by line, so statement i is wrong. Computer architecture means the attributes of a system visible to the programmer. RISC cuts the cycles per instruction at the cost of more instructions per program, and the arithmetic and logical work is done by the ALU under the control unit. So i-False, ii-True, iii-True and iv-True is correct.

Discuss in Forum

A processor has 64 general-purpose registers and 50 distinct instruction types. An instruction is encoded in 32-bits. What is the maximum number of bits that can be used to store the immediate operand for the given instruction?

ADD R1, #25 // R1 = R1 + 25

A.16
B.20
C.22
D.24

Exam Year(s)

GATE CS - 2025,

Answer: B

At most 20 bits are left for the immediate operand.

The instruction ADD R1, #25 has three fields: the opcode, one register and the immediate value.

\[ \begin{aligned} \text{opcode} &= \lceil \log_{2} 50 \rceil = 6\ \text{bits} \\ \text{register} &= \log_{2} 64 = 6\ \text{bits} \\ \text{immediate} &= 32 - 6 - 6 = 20\ \text{bits} \end{aligned} \]

Five bits would allow only 32 instruction types, so six are needed for 50. 16 bits would set aside 4 more bits than the instruction's fields need, while 22 and 24 bits would leave only 10 or 8 bits for the opcode and register together, too few to encode 50 instruction types and 64 registers.

Discuss in Forum

Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the first operand of any instruction is the destination operand.

Which one of the following sequences of instructions corresponds to the high-level language statement Z = X + Y ?

Note: X, Y, and Z are memory operands. R0, R1, and R2 are registers.

A.ADD Z, X, Y
B.LOAD R0, X / ADD Z, R0, Y
C.ADD R0, X, Y / STORE Z, R0
D.LOAD R0, X / LOAD R1, Y / ADD R2, R0, R1 / STORE Z, R2

Exam Year(s)

GATE CS - 2026,

Answer: D

The correct sequence is LOAD R0, X / LOAD R1, Y / ADD R2, R0, R1 / STORE Z, R2.

In a load-store architecture only LOAD and STORE may access memory; arithmetic instructions work on registers only. So both operands must first be loaded into registers, added register to register, and the result stored back to Z.

ADD Z, X, Y uses three memory operands. 'LOAD R0, X / ADD Z, R0, Y' still has the ADD reading Y from memory and writing Z to memory. 'ADD R0, X, Y / STORE Z, R0' has the ADD reading X and Y from memory. Each breaks the load-store rule.

Discuss in Forum

Which of the following is/are part of an Instruction Set Architecture of a processor?

A.The size of the cache memory
B.The clock frequency of the processor
C.The number of cache memory levels
D.The total number of registers

Exam Year(s)

GATE CS - 2025,

Answer: D

Only the total number of registers is part of the Instruction Set Architecture.

The ISA is the interface between hardware and software: everything a machine-language programmer or compiler must know, such as the instructions, addressing modes, data types and the programmer-visible registers. Instructions name registers in their operand fields, so the number of registers is fixed by the ISA.

The size of the cache, the number of cache levels and the clock frequency are properties of a particular implementation (the microarchitecture). Two processors with the same ISA can differ in all three and still run the same programs unchanged, which is why none of them is part of the ISA.

Discuss in Forum

Consider a processor that has 16 general purpose registers and it uses 2-byte instruction format for all its instructions. Variable-sized opcodes are permitted. There are three different types of instructions; M-type, R-type, and C-type. Each M-type instruction has 2 register operands and a 6-bit immediate operand. Each R-type instruction has 3 register operands. Each C-type instruction has a register operand and a 6-bit offset value. If there are 2 unique M-type opcodes and 7 unique R-type opcodes, which one of the following options gives the maximum number of unique opcodes possible for C-type instructions?

A.8
B.4
C.64
D.16

Exam Year(s)

GATE CS - 2026,

Answer: B

The maximum number of C-type opcodes is 4.

Each instruction is 16 bits, and with 16 registers a register field needs 4 bits. The bits left for the opcode in each type:

M-type: 2 registers + 6-bit immediate = 14 bits, leaving a 2-bit opcode;
R-type: 3 registers = 12 bits, leaving 4 bits;
C-type: 1 register + 6-bit offset = 10 bits, leaving 6 bits.

With an expanding opcode, the 2-bit field gives 4 patterns. M-type uses 2; the other 2 become prefixes for longer opcodes. Extending each by 2 bits gives 2 × 4 = 8 four-bit patterns. R-type uses 7, leaving 1 as a prefix. Extending it by the last 2 bits gives 4 six-bit patterns, so C-type can have at most 4 opcodes.

64 would be the count if the whole 6-bit field were free, and 16 or 8 forget that the M-type and R-type opcodes have already used up most of the prefixes.

Discuss in Forum

Consider the following processor design characteristics.

I. Register-to-register arithmetic operations only
II. Fixed-length instruction format
III. Hardwired control unit

Which of the characteristics above are used in the design of a RISC processor?

A.I and II only
B.II and III only
C.I and III only
D.I, II and III

Exam Year(s)

GATE CS - 2018,

Answer: D

All three are RISC characteristics, so the answer is I, II and III.

A RISC processor is a load-store machine: arithmetic works only on registers, and memory is reached only by load and store instructions (I). Its instructions have a fixed length, usually one word, which makes fetching and decoding simple and pipelining easy (II). With a small set of simple instructions, the control unit can be hardwired rather than microprogrammed, which is faster (III).

Each two-item option leaves out one of these, so none of them is complete. Variable-length instructions, memory operands in arithmetic and microprogrammed control are the CISC features they contrast with.

Discuss in Forum

Consider the given C-code and its corresponding assembly code, with a few operands U1-U4 being unknown. Some useful information as well as the semantics of each unique assembly instruction is annotated as inline comments in the code. The memory is byte-addressable.
//C-code int a[10], b[10], i; // int is 32-bit for (i=0; i\(\lt\)10;i++) a[i] = b[i] * 8; ;assembly-code (; indicates comments) ;r1-r5 are 32-bit integer registers ;initialize r1=0, r2=10 ;initialize r3, r4 with base address of a, b L01: jeq r1, r2, end ;if(r1==r2) goto end L02: lw r5, 0(r4) ;r5 \(\lt\)- Memory[r4+0] L03: shl r5, r5, U1 ;r5 \(\lt\)- r5 \(\lt\lt\) U1 L04: sw r5, 0(r3) ;Memory[r3+0] \(\lt\)- r5 L05: add r3, r3, U2 ;r3 \(\lt\)- r3+U2 L06: add r4, r4, U3 L07: add r1, r1, 1 L08: jmp U4 ;goto U4 L09: end
Which one of the following options is a CORRECT replacement for operands in the position (U1, U2, U3, U4) in the above assembly code?

A.(8, 4, 1, L02)
B.(3, 4, 4, L01)
C.(8, 1, 1, L02)
D.(3, 1, 1, L01)

Exam Year(s)

GATE CS - 2023,

Answer: B

The operands are (3, 4, 4, L01).

U1: multiplying by 8 is a left shift by 3 bits, since \(8 = 2^{3}\). A shift of 8 would multiply by 256.
U2 and U3: an int is 32 bits, 4 bytes, and memory is byte-addressable, so the pointers r3 (into a) and r4 (into b) must each advance by 4 to reach the next element.
U4: after r1 is incremented, the loop must test r1 == r2 again before the next iteration, so it jumps back to L01. Jumping to L02 skips the test and never leaves the loop.

(8, 4, 1, L02) gets the shift, the b pointer and the jump wrong; (8, 1, 1, L02) also steps the pointers by a single byte; and (3, 1, 1, L01) has the right shift and jump but moves only one byte per element, reading and writing overlapping parts of the integers.

Discuss in Forum

Loading…

Topics

Other Subjects

Tags: Instruction Set Architecture Questions and Answers || Instruction Set Architecture MCQ Questions and Answers || Instruction Set Architecture GK Questions and Answers || Instruction Set Architecture GK MCQ Questions || Instruction Set Architecture Multiple Choice Questions and Answers || Instruction Set Architecture GK || GK on Instruction Set Architecture || Computer Organization and Architecture Questions and Answers || Computer Organization and Architecture MCQ Questions and Answers || Computer Organization and Architecture GK Questions and Answers || GK on Computer Organization and Architecture

Instruction Set Architecture Questions and Answers

Topics

Other Subjects

About Us

Stay informed about all important Dates & Notifications