Field Effect Transistors Questions and Answers

Q: Why is an insulated-gate bipolar device used instead of a MOSFET at high voltage?

A high-voltage MOSFET needs a thick drift region, and its on-resistance rises steeply with the voltage rating, so the quadratic loss law becomes punitive - whereas a bipolar-output device keeps a roughly constant drop of a couple of volts. Its gate charge is comparable or larger, it switches more slowly rather than faster, and its gate is a MOSFET gate so the input impedance is the same. Combining a MOSFET input with a bipolar output takes the voltage-driven gate and the constant conducting drop together, which is exactly the compromise high-voltage switching wants.

Q: In a N-type channel, VGS = 0 and VDS is increased, which of the following does not happen?

The Board's key is D, depletion region decreases: that is the statement that does not happen.In an n-channel JFET with \(V_{GS} = 0\), raising \(V_{DS}\) reverse-biases the gate-channel junction more strongly toward the drain end. The depletion region therefore widens and narrows the channel, so option A does happen. The drain current rises with \(V_{DS}\) at first, then levels off at a limited value (the saturation current \(I_{DSS}\)) once the channel pinches off, so option C does happen.Option D, a shrinking depletion region, is the opposite of what the rising reverse bias does, and the key rests on that. Option B, a decrease in drain current, does not happen either in the textbook picture, because the current rises and then holds constant; the item therefore has two statements that fail to happen, and the official key keeps only D.

Q: The voltage of a common source JFET amplifier depends upon its __________.

The voltage gain depends on both transconductance and internal load resistance.A JFET is controlled by its gate-source voltage, and its transconductance \(g_{m}\) gives the change in drain current per volt of input. That current flows through the drain load, so the output voltage is the current times the load resistance, giving a gain of about \(A_{v} = g_{m} r_{L}\), where \(r_{L}\) is the effective drain load (the drain resistor in parallel with the device's own drain resistance).Transconductance alone or load resistance alone gives only one factor of the product. The amplification factor is a device constant, the gain with an unlimited load, and does not describe a working stage with a finite load.

Q: \(I_{D}\) and \(V_{GS}\) notations in a FET denote the following parameters :

\(I_{D}\) and \(V_{GS}\) denote DC values.The standard notation uses the case of the symbol and of its subscript: an upper-case symbol with an upper-case subscript (\(I_{D}\), \(V_{GS}\)) is the quiescent DC value; lower-case with upper-case subscript (\(i_{D}\), \(v_{GS}\)) is the total instantaneous value; lower-case with lower-case subscript (\(i_{d}\), \(v_{gs}\)) is the instantaneous ac component; and upper-case with lower-case subscript (\(I_{d}\), \(V_{gs}\)) is the rms or phasor value of the ac component.So the other three options correspond to the other three combinations of letter case, not to the notation in the question.

Q: Compared to BJT, a JFET has :

Compared to a BJT, a JFET has higher input impedance and low voltage gain.The JFET's gate-source junction is reverse biased, so almost no gate current flows and the input impedance is very high, typically many megohms, against the kilohms of a BJT's forward-biased base-emitter junction.Its transconductance is much lower than a BJT's at the same current, so a JFET amplifier usually gives lower voltage gain. That rules out 'lower input impedance', 'higher voltage gain' and the option pairing high input impedance with high gain.

Q: Estimate VGS in the following circuit :(Figure: an n-channel MOSFET whose gate and drain are both connected to the 5 V supply; its source is connected to ground through a 7 K resistor, and a current of 0.3 mA flows down through that resistor.)

\(V_{GS}\) is about 2.9 V.The gate is tied to the 5 V supply, so \(V_{G} = 5\) V. The source voltage is the drop across the 7 K resistor carrying 0.3 mA.\[ \begin{aligned} V_{S} &= 0.3\ \text{mA} \times 7\ \text{k}\Omega = 2.1\ \text{V} \\ V_{GS} &= V_{G} - V_{S} = 5 - 2.1 = 2.9\ \text{V} \end{aligned} \]The other values would need different source voltages: 4.9 V a drop of only 0.1 V across the resistor, 3.5 V a drop of 1.5 V, and 1.5 V a drop of 3.5 V. None matches 0.3 mA through 7 kΩ.

101.

How does paralleling two such devices affect the total conduction loss?

A.It halves the loss for the same total current
B.It leaves the loss unchanged, since the current divides
C.It doubles the loss
D.It quarters the loss, by halving both current and resistance

Answer: A

Each device carries half the current through the same resistance, so each dissipates a quarter as much, and two of them together dissipate half the original figure. That the saving is a factor of two rather than four is the point worth being careful about: the quadratic law helps, but there are two devices sharing. Leaving the loss unchanged would be true of a constant-voltage-drop device instead, which is another way the two families differ. And self-correcting current sharing is what makes the arrangement safe to attempt in the first place.

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102.

Why is an insulated-gate bipolar device used instead of a MOSFET at high voltage?

A.Its input impedance is higher than a MOSFET's gate offers
B.Its conducting drop grows more slowly with current
C.Its gate charge is smaller than a MOSFET's of the same rating
D.It switches faster than a MOSFET at every voltage rating

Answer: B

A high-voltage MOSFET needs a thick drift region, and its on-resistance rises steeply with the voltage rating, so the quadratic loss law becomes punitive - whereas a bipolar-output device keeps a roughly constant drop of a couple of volts. Its gate charge is comparable or larger, it switches more slowly rather than faster, and its gate is a MOSFET gate so the input impedance is the same. Combining a MOSFET input with a bipolar output takes the voltage-driven gate and the constant conducting drop together, which is exactly the compromise high-voltage switching wants.

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103.

The transconductance curve for the D-MOSFET is very similar to the curve for a ______.

A.BJT
B.PN junction diode
C.SCR
D.JFET

Exam Year(s)

DSSSB AE - 2023,

Answer: D

The transfer (transconductance) curve of a depletion type MOSFET, which plots drain current against gate to source voltage, follows the same Shockley relation as a JFET, \(I_D = I_{DSS}(1 - V_{GS}/V_P)^2\), and in the depletion mode it looks very much like the JFET curve; the difference is that the D-MOSFET also continues into the enhancement region with positive gate voltage.

A BJT has an exponential relation between base voltage and current, a PN junction diode has an exponential current voltage curve, and an SCR is a switching device with no such transfer curve. The answer is JFET, option D.

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104.

Which of the following biasing techniques is NOT commonly used in case of E-MOSFET?

A.Gate bias
B.Voltage-divider bias
C.Drain feedback bias
D.Zero bias

Exam Year(s)

DSSSB AE - 2023,

Answer: D

An enhancement type MOSFET conducts only when the gate voltage exceeds the threshold, in the same polarity as the drain. So it needs a gate voltage above threshold, which is supplied by gate bias (a fixed supply), voltage divider bias or drain feedback bias, where the gate is connected to the drain.

Zero bias, where the gate is held at 0 V (as can be done with a JFET or a depletion MOSFET), would leave an E-MOSFET switched off, since \(V_{GS} = 0\) is below the threshold. That is why zero bias is not used with it. The answer is option D.

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105.

For an N-channel depletion type MOSFET, the value of drain current at zero \(V_{GS}\) (gate to source voltage), \(I_{DSS} = 10\) mA. What is the value of drain current at \(V_{GS} = +1\) V? The value of pinch off voltage \(V_P = -4\) V.

A.1.563 mA
B.15.63 mA
C.156.3 mA
D.0.1563 mA

Exam Year(s)

DSSSB AE - 2023,

Answer: B

The drain current of a depletion type MOSFET follows the Shockley equation

\[ I_D = I_{DSS}\left(1 - \frac{V_{GS}}{V_P}\right)^2 \]

\[ \begin{aligned} I_D = 10\left(1 - \frac{1}{-4}\right)^2 \\ &= 10\left(1 + 0.25\right)^2 = 10 \times 1.5625 \\ &= 15.63\ \text{mA} \end{aligned} \]

The depletion MOSFET can work with a positive gate voltage (enhancement mode), so the current is greater than \(I_{DSS}\). The value 1.563 mA is a factor of ten too small, 156.3 mA is a factor of ten too large, and 0.1563 mA is a hundred times too small. The answer is option B.

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106.

In a N-type channel, V_GS = 0 and V_DS is increased, which of the following does not happen?

A.Depletion region increases
B.Decrease in drain current
C.\(I_{D}\) reaches a limited value
D.Depletion region decreases

Exam Year(s)

RSMSSB JE - 2025, RSMSSB - 2025,

Answer: D

The Board's key is D, depletion region decreases: that is the statement that does not happen.

In an n-channel JFET with \(V_{GS} = 0\), raising \(V_{DS}\) reverse-biases the gate-channel junction more strongly toward the drain end. The depletion region therefore widens and narrows the channel, so option A does happen. The drain current rises with \(V_{DS}\) at first, then levels off at a limited value (the saturation current \(I_{DSS}\)) once the channel pinches off, so option C does happen.

Option D, a shrinking depletion region, is the opposite of what the rising reverse bias does, and the key rests on that. Option B, a decrease in drain current, does not happen either in the textbook picture, because the current rises and then holds constant; the item therefore has two statements that fail to happen, and the official key keeps only D.

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107.

The voltage of a common source JFET amplifier depends upon its __________.

A.both transconductance and internal load resistance
B.transconductance
C.amplification factor
D.internal load resistance

Exam Year(s)

RSMSSB JE - 2025, RSMSSB - 2025,

Answer: A

The voltage gain depends on both transconductance and internal load resistance.

A JFET is controlled by its gate-source voltage, and its transconductance \(g_{m}\) gives the change in drain current per volt of input. That current flows through the drain load, so the output voltage is the current times the load resistance, giving a gain of about \(A_{v} = g_{m} r_{L}\), where \(r_{L}\) is the effective drain load (the drain resistor in parallel with the device's own drain resistance).

Transconductance alone or load resistance alone gives only one factor of the product. The amplification factor is a device constant, the gain with an unlimited load, and does not describe a working stage with a finite load.

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108.

\(I_{D}\) and \(V_{GS}\) notations in a FET denote the following parameters :

A.Total instantaneous values
B.Instantaneous ac values
C.Phasor values
D.DC values

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: D

\(I_{D}\) and \(V_{GS}\) denote DC values.

The standard notation uses the case of the symbol and of its subscript: an upper-case symbol with an upper-case subscript (\(I_{D}\), \(V_{GS}\)) is the quiescent DC value; lower-case with upper-case subscript (\(i_{D}\), \(v_{GS}\)) is the total instantaneous value; lower-case with lower-case subscript (\(i_{d}\), \(v_{gs}\)) is the instantaneous ac component; and upper-case with lower-case subscript (\(I_{d}\), \(V_{gs}\)) is the rms or phasor value of the ac component.

So the other three options correspond to the other three combinations of letter case, not to the notation in the question.

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109.

Compared to BJT, a JFET has :

A.Lower input impedance
B.Higher voltage gain
C.Higher input impedance and high voltage gain
D.Higher input impedance and low voltage gain

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: D

Compared to a BJT, a JFET has higher input impedance and low voltage gain.

The JFET's gate-source junction is reverse biased, so almost no gate current flows and the input impedance is very high, typically many megohms, against the kilohms of a BJT's forward-biased base-emitter junction.

Its transconductance is much lower than a BJT's at the same current, so a JFET amplifier usually gives lower voltage gain. That rules out 'lower input impedance', 'higher voltage gain' and the option pairing high input impedance with high gain.

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110.

Estimate V_GS in the following circuit :

(Figure: an n-channel MOSFET whose gate and drain are both connected to the 5 V supply; its source is connected to ground through a 7 K resistor, and a current of 0.3 mA flows down through that resistor.)

A.1.5 V
B.4.9 V
C.3.5 V
D.2.9 V

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: D

\(V_{GS}\) is about 2.9 V.

The gate is tied to the 5 V supply, so \(V_{G} = 5\) V. The source voltage is the drop across the 7 K resistor carrying 0.3 mA.

\[ \begin{aligned} V_{S} &= 0.3\ \text{mA} \times 7\ \text{k}\Omega = 2.1\ \text{V} \\ V_{GS} &= V_{G} - V_{S} = 5 - 2.1 = 2.9\ \text{V} \end{aligned} \]

The other values would need different source voltages: 4.9 V a drop of only 0.1 V across the resistor, 3.5 V a drop of 1.5 V, and 1.5 V a drop of 3.5 V. None matches 0.3 mA through 7 kΩ.

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