Instruction Set Architecture Questions and Answers

Answer: B

Statement i is false and statements ii, iii and iv are true. A compiler translates the whole source program at once into machine code, and it is an interpreter that works line by line, so statement i is wrong. Computer architecture means the attributes of a system visible to the programmer. RISC cuts the cycles per instruction at the cost of more instructions per program, and the arithmetic and logical work is done by the ALU under the control unit. So i-False, ii-True, iii-True and iv-True is correct.

Answer: B

At most 20 bits are left for the immediate operand.

The instruction ADD R1, #25 has three fields: the opcode, one register and the immediate value.

\[ \begin{aligned} \text{opcode} &= \lceil \log_{2} 50 \rceil = 6\ \text{bits} \\ \text{register} &= \log_{2} 64 = 6\ \text{bits} \\ \text{immediate} &= 32 - 6 - 6 = 20\ \text{bits} \end{aligned} \]

Five bits would allow only 32 instruction types, so six are needed for 50. 16 bits would set aside 4 more bits than the instruction's fields need, while 22 and 24 bits would leave only 10 or 8 bits for the opcode and register together, too few to encode 50 instruction types and 64 registers.

Answer: D

The correct sequence is LOAD R0, X / LOAD R1, Y / ADD R2, R0, R1 / STORE Z, R2.

In a load-store architecture only LOAD and STORE may access memory; arithmetic instructions work on registers only. So both operands must first be loaded into registers, added register to register, and the result stored back to Z.

ADD Z, X, Y uses three memory operands. 'LOAD R0, X / ADD Z, R0, Y' still has the ADD reading Y from memory and writing Z to memory. 'ADD R0, X, Y / STORE Z, R0' has the ADD reading X and Y from memory. Each breaks the load-store rule.

Answer: D

Only the total number of registers is part of the Instruction Set Architecture.

The ISA is the interface between hardware and software: everything a machine-language programmer or compiler must know, such as the instructions, addressing modes, data types and the programmer-visible registers. Instructions name registers in their operand fields, so the number of registers is fixed by the ISA.

The size of the cache, the number of cache levels and the clock frequency are properties of a particular implementation (the microarchitecture). Two processors with the same ISA can differ in all three and still run the same programs unchanged, which is why none of them is part of the ISA.

Answer: B

The maximum number of C-type opcodes is 4.

Each instruction is 16 bits, and with 16 registers a register field needs 4 bits. The bits left for the opcode in each type:

• M-type: 2 registers + 6-bit immediate = 14 bits, leaving a 2-bit opcode;
• R-type: 3 registers = 12 bits, leaving 4 bits;
• C-type: 1 register + 6-bit offset = 10 bits, leaving 6 bits.

With an expanding opcode, the 2-bit field gives 4 patterns. M-type uses 2; the other 2 become prefixes for longer opcodes. Extending each by 2 bits gives 2 × 4 = 8 four-bit patterns. R-type uses 7, leaving 1 as a prefix. Extending it by the last 2 bits gives 4 six-bit patterns, so C-type can have at most 4 opcodes.

64 would be the count if the whole 6-bit field were free, and 16 or 8 forget that the M-type and R-type opcodes have already used up most of the prefixes.

Answer: D

All three are RISC characteristics, so the answer is I, II and III.

A RISC processor is a load-store machine: arithmetic works only on registers, and memory is reached only by load and store instructions (I). Its instructions have a fixed length, usually one word, which makes fetching and decoding simple and pipelining easy (II). With a small set of simple instructions, the control unit can be hardwired rather than microprogrammed, which is faster (III).

Each two-item option leaves out one of these, so none of them is complete. Variable-length instructions, memory operands in arithmetic and microprogrammed control are the CISC features they contrast with.

Answer: B

The operands are (3, 4, 4, L01).

• U1: multiplying by 8 is a left shift by 3 bits, since \(8 = 2^{3}\). A shift of 8 would multiply by 256.
• U2 and U3: an int is 32 bits, 4 bytes, and memory is byte-addressable, so the pointers r3 (into a) and r4 (into b) must each advance by 4 to reach the next element.
• U4: after r1 is incremented, the loop must test r1 == r2 again before the next iteration, so it jumps back to L01. Jumping to L02 skips the test and never leaves the loop.

(8, 4, 1, L02) gets the shift, the b pointer and the jump wrong; (8, 1, 1, L02) also steps the pointers by a single byte; and (3, 1, 1, L01) has the right shift and jump but moves only one byte per element, reading and writing overlapping parts of the integers.