Logic Gates Questions and Answers

Answer: A

A positive-logic OR gate functions as an AND gate in negative logic.

In positive logic, high = 1 and low = 0, and an OR gate gives a high output whenever any input is high, so its output is low only when all inputs are low. In negative logic the meanings flip: low = 1 and high = 0. Read that way, the same gate gives an output of 1 (low) only when all inputs are 1 (low), which is the AND function.

This is De Morgan's duality in hardware: \(\overline{A + B} = \overline{A}\cdot\overline{B}\). The gate does not invert, so it cannot become NAND, NOR or NOT by a change of logic convention alone.

Answer: D

The truth table has 8 entries.

Each input can be 0 or 1, so n inputs give 2ⁿ combinations. For three inputs, 2³ = 8 rows, from 000 to 111. For a NAND gate the output is 0 only in the row 111 and 1 in the other seven.

3 counts the inputs rather than the combinations, 6 is 2 × 3, and 9 is 3², none of which is the number of binary input combinations.

Answer: D

The output is \( Y = X_{0}X_{1}X_{3}\ldots X_{n-1} + X_{2}X_{3}X_{5}\ldots X_{n-1} \) \( + \ldots + X_{n-2}X_{n-1} + X_{n} \).

The gates alternate AND and OR. Work along the chain:

\[ \begin{aligned} G_{1} &= X_{0}X_{1} \\ G_{2} &= X_{0}X_{1} + X_{2} \\ G_{3} &= X_{0}X_{1}X_{3} + X_{2}X_{3} \end{aligned} \]

Each AND gate multiplies every existing term by its new input, and each OR gate adds its input as a new term. Every term therefore carries all the AND-gate inputs after it (\( X_{3}, X_{5}, \ldots, X_{n-1} \)), and the final OR adds \( X_{n} \) alone.

All-OR, \( X_{0} + X_{1} + \ldots + X_{n} \), would need every gate to be an OR. The sum of pairs ignores the cascading, and the first option multiplies in inputs such as \( X_{2} \) and \( X_{n} \) that enter through OR gates.

Answer: B

The output is (A + B)C + DE.

Trace the gates. The OR gate gives A + B. The first NAND gate gives X = NOT((A + B)C). The AND gate and inverter give Y = NOT(DE). The final NAND gate gives:

\[ \begin{aligned} \overline{X \cdot Y} &= \overline{X} + \overline{Y} \\ &= (A + B)C + DE \end{aligned} \]

by De Morgan's theorem, since each inverted term is inverted back. The option (A + B)C + D + E forgets that D and E pass through an AND gate, and the other options mix up the OR and AND stages.

Answer: B

The output of an EX-NOR gate is High.

EX-NOR is the complement of EX-OR. An EX-OR gate gives 1 when an odd number of its inputs are 1 (it is an odd-parity detector), so the EX-NOR gives 1 when the number of 1s is even, including the case of all inputs 0 (zero 1s, which is even).

For two inputs: 00 gives 1, 01 and 10 give 0, 11 gives 1. So the output is not Low, and it is perfectly defined.

Answer: A

The most suitable gates are EX-OR gates.

The output of an exclusive-OR is 1 when an odd number of its inputs are 1. Chaining EX-OR gates across all the bits of a word (\(b_{0} \oplus b_{1} \oplus \dots \oplus b_{n}\)) therefore gives 1 if the number of ones is odd and 0 if it is even. This is how parity generators and parity checkers are built, for example in the 74180 and 74280 chips.

NAND and NOR are universal gates, so a parity circuit could in principle be built from them, but only by first making EX-OR functions from several gates each. AND and OR alone cannot detect parity, since they cannot tell two ones from one.

Answer: D

The function is F = ABC.

Write the output of each gate:

\[ \begin{aligned} \text{OR gate} &: A + \bar{B} \\ \text{lower AND} &: BC \\ F &= (A + \bar{B})BC \end{aligned} \]

Expanding,

\[ F = ABC + \bar{B}BC = ABC + 0 = ABC \]

since \(B\bar{B} = 0\). The first option forgets the inverter on B and uses an OR in the wrong place, the second treats the final AND gate as an OR, and BC(B + A) simplifies to BC, which is true even when A is 0, unlike the network.

Answer: A

The circuit is a half-subtractor.

Reading the gates:

\[ \begin{aligned} X_{out} &= A\bar{B} + \bar{A}B = A \oplus B \\ Y_{out} &= \bar{A}B \end{aligned} \]

For the subtraction A - B of two bits, the difference is \(A \oplus B\) and a borrow is needed only when A = 0 and B = 1, which is \(\bar{A}B\). So \(X_{out}\) is the difference and \(Y_{out}\) the borrow.

A half-adder has the same XOR output but its second output, the carry, is AB, not \(\bar{A}B\). Nothing in the circuit switches between adding and subtracting, so it is neither a half-adder/subtractor nor a 2's complement adder/subtractor.

Answer: D

The gate gives the truth table A = 0, Q = 1; A = 1, Q = 0.

A NOR gate outputs 1 only when all its inputs are 0. With both inputs tied to A, the output is \(\overline{A + A} = \overline{A}\), so the gate acts as an inverter: A = 0 gives Q = 1, and A = 1 gives Q = 0.

Option A is a constant 0, option B a constant 1, and option C is a buffer (Q = A), none of which a NOR gate with tied inputs produces.

Answer: C

The complement in a NOR symbol is shown by a small circle.

A NOR gate is an OR gate followed by inversion, and its symbol is the OR shape with a small circle, called a bubble, at the output. The same bubble marks inversion everywhere in logic symbols: on the output of NAND and NOT gates, and on inputs that are active-low.

The triangle is the body of the buffer and NOT symbols, not a mark of complement. Squares and diamonds are not used to show inversion in the standard gate symbols. A NOR is simply 'NOT OR', so the bubble that turns the OR symbol into a NOR is the graphic mark of its complement nature.