Counters Questions and Answers

Answer: B

In a ripple counter each flipflop is clocked by the output of the one before it, so the delays add up. For four stages

\[ t_{total} = 4 \times 25\ \text{ns} = 100\ \text{ns} \]

The clock period must be at least the total delay, so the highest clock frequency is

\[ f = \frac{1}{100 \times 10^{-9}} = 10\ \text{MHz} \]

The value 100 MHz is the frequency for a single flipflop of 10 ns, and 1 MHz and 100 kHz are far below the limit. The answer is 10 MHz, option B.

Answer: D

A 4 bit counter counts in the binary sequence, each count adding one to the previous output. Starting at 0000, the outputs are 0001, 0010, 0011 and then 0100.

\[ 0000 \to 0001 \to 0010 \to 0011 \to 0100 \]

The value 0100 is the decimal number 4, so it takes 4 counts, whether the counter is asynchronous (ripple) or synchronous, since the sequence of the outputs is the same; the difference is in the timing. The answer is 4, option D.

Answer: D

A decade counter counts ten states, 0000 to 1001 (0 to 9), and then resets. The number of flip flops \(n\) must satisfy \(2^n \ge 10\).

\[ 2^3 = 8 \lt 10,\qquad 2^4 = 16 \ge 10 \]

So three flip flops give only 8 states, which is not enough, and four are needed. The counter is a mod 10 counter built with 4 JK flip flops and the extra states 1010 to 1111 are not used. The answer is 4, option D.

Answer: A

A ripple counter is a cascaded arrangement of flip-flops in which the output of one flip-flop drives the clock input of the next, so the change ripples through the chain. In a synchronous counter all flip-flops share one clock. A ring counter is a shift register whose last output is fed back to the first input. 'Cascaded counter' is not the standard name for this arrangement. It is called a ripple counter because the change in one stage moves on, stage by stage, like a ripple, and so it is also called an asynchronous counter.

Answer: A

The state that can never occur is (0, 0, 1).

All three flip-flops share CLKIN. From the figure, the first T input is \(\overline{Q3}\), the D input is Q1, and the second T input is Q2. So at each clock edge:

\[ \begin{aligned} Q1^{+} &= Q1 \oplus \overline{Q3} \\ Q2^{+} &= Q1 \\ Q3^{+} &= Q3 \oplus Q2 \end{aligned} \]

Starting from (0, 1, 1), the states run 011, 000, 100, 010, 101, 111, 110, and then back to 011. That cycle holds seven of the eight states; the missing one is 001.

(1, 0, 0) appears after the second clock, (1, 0, 1) after the fourth and (1, 1, 1) after the fifth, so they can all be obtained.