Multiplexers and Decoders Questions and Answers

Answer: D

The output is \(X = \bar{Q}\bar{R} + PQR\).

A 2-to-1 MUX outputs input 0 when its select line is 0 and input 1 when it is 1. The first MUX outputs 0 when \(P = 0\) and \(R\) when \(P = 1\), so its output is \(PR\). The second MUX outputs \(\bar{R}\) when \(Q = 0\) and the first MUX's output \(PR\) when \(Q = 1\):

\[ X = \bar{Q}\bar{R} + Q(PR) = \bar{Q}\bar{R} + PQR \]

The two terms cannot be merged (one needs \(Q = 0\), the other \(Q = 1\)), so this is already minimal. Test values rule out the others: for \(P = 1, Q = 0, R = 0\) the circuit gives \(X = \bar{R} = 1\), but \(\bar{P}\bar{Q} + PQR\) and \(PQ + \bar{P}\bar{Q}R\) both give 0; for \(P = 0, Q = 1, R = 1\) the circuit gives 0, but \(\bar{P}Q + QR\) gives 1.

Answer: C

P is a 10:\(2^{10}\) decoder, Q is a 5:\(2^{5}\) decoder and T is a 2:1 multiplexer.

S holds 1024 = \(2^{10}\) words, so its address field has 10 bits, and P must turn those 10 bits into one select line out of 1024: that is a 10-to-\(2^{10}\) decoder. R holds 32 = \(2^{5}\) words, so Q turns 5 address bits into one of 32 select lines, a 5-to-\(2^{5}\) decoder. T has two data inputs, the word from S and the word from R, and the mode bit M chooses which one is passed to X; choosing one of two inputs under a select signal is a 2:1 multiplexer.

A 10:1 multiplexer picks one of ten inputs, which does not address 1024 words. An encoder converts one active line into a code, which is not what T does. A 1:10 de-multiplexer routes one input to ten outputs, again not an address decoder for 1024 locations.

Answer: B

The circuit is equivalent to a D latch.

The output Q is fed back to input 0, the external data line goes to input 1, and S selects between them:

• S = 1: Q follows input 1, so the output tracks the data while S is high (the latch is transparent).
• S = 0: Q takes input 0, which is Q itself, so the output holds its last value.

Following the data while an enable is high and holding it while the enable is low is a level-sensitive D latch, with S as the enable. A D flip-flop changes only on a clock edge, which needs two latches in a master-slave arrangement. A half-adder has two outputs, sum and carry, and no memory, and a demultiplexer routes one input to one of several outputs.

Answer: C

The inputs are (1, 1, 0, 1, 1, 1, 0, 0).

First simplify the function. \(\overline{A}.\overline{C}\) is already covered by \(\overline{A}\), and \(\overline{A} + A.\overline{B}.C = \overline{A} + \overline{B}.C\):

\[ F = \overline{A} + \overline{B}C \]

M3 chooses M1 when B = 0 and M2 when B = 1. Both 4-input multiplexers select their input by (S1, S0) = (A, C).

• B = 0: F = \(\overline{A} + C\). AC = 00, 01, 10, 11 gives X0..X3 = 1, 1, 0, 1.
• B = 1: F = \(\overline{A}\). AC = 00, 01, 10, 11 gives X4..X7 = 1, 1, 0, 0.

The first option puts 0 in X3 and 1 in X6, the second puts 0 in X3 and 1 in X7, and the last sets X0 and X1 to 0, although F = 1 whenever A = 0.

Answer: A

The correct implementation is circuit (A).

A 2-to-1 multiplexer computes

\[ X = A_{0}\bar{C} + A_{1}C \]

so one AND gate must pass \(A_{0}\) when \(C = 0\), which needs \(C\) inverted at that gate, and the other must pass \(A_{1}\) when \(C = 1\), with \(C\) uninverted. An OR gate combines them. Circuit (A) has the inversion bubble on the \(C\) input of the \(A_{0}\) gate: exactly this.

Circuit (B) inverts \(C\) at the \(A_{1}\) gate, so it selects \(A_{1}\) when \(C = 0\), the reverse of the specification. Circuit (D) has no inversion, so both gates are enabled together by \(C = 1\) and both disabled by \(C = 0\). Circuit (C) uses OR gates in the first stage, which pass a 1 whenever either input is 1, so it cannot select one input.