Match the List I with List II and select the correct answer using the codes given below it :List IList II(a) SRAM(1) Floating gate MOSFET(b) DRAM(2) Flip-Flop(c) Flash Memory(3) Magnetic(d) Hard Disk(4) MOSFETCodes : (a) (b) (c) (d)

The correct code is (2) (4) (1) (3).(a) SRAM stores each bit in a flip-flop (a latch of cross-coupled transistors).(b) DRAM stores each bit as charge on a capacitor accessed through a MOSFET.(c) Flash memory stores charge on the floating gate of a floating-gate MOSFET.(d) A hard disk stores data magnetically.Option B gives flash memory the magnetic storage of the hard disk, and options A and D misplace SRAM and DRAM.

Memory Devices Questions and Answers

Q: Address and Data lines required to access 32 kB, byte organised memory will be :

The memory needs 15 address lines and 8 data lines.A byte-organised memory stores one 8-bit byte at each address, so it needs 8 data lines. The number of address lines n must satisfy \(2^{n} = \) number of locations:\[ \begin{aligned} 32\ \text{kB} &= 32 \times 1024 \\ &= 2^{5} \times 2^{10} = 2^{15} \end{aligned} \]so 15 address lines are needed. 12 and 13 address lines would reach only 4 kB and 8 kB, and '32 and 1' confuses the capacity with the number of lines.

Q: The minimum time required for memory device to put valid data on the data bus after CS goes low is called :

The answer is tACS : Chip select access time.In memory timing, tACS is measured from the moment chip select (CS) goes active (low) to the moment valid data appears on the data bus. It is the minimum time the processor must wait after selecting the chip before it can read.tAA (address access time) is measured from a stable address, not from CS. tLZ is the time from chip select until the outputs leave the high-impedance state (they are driven but not yet valid), and tHZ is the time for the outputs to return to tri-state after deselection.

Q: An amount of memory required to store a 256 gray shade monochrome image with 512 × 512 resolution will be :

The memory needed is 256 K bytes.256 grey shades need 8 bits per pixel, since \(2^{8} = 256\), which is one byte per pixel.\[ \begin{aligned} 512 \times 512 &= 262144 \text{ pixels} \\ &= 262144 \text{ bytes} \\ &= 256 \times 1024 = 256\ \text{K bytes} \end{aligned} \]512 K bytes would mean 16 bits per pixel, 1 M byte 32 bits, and 64 K bytes only 2 bits per pixel (4 grey levels).

Q: The word size of memory IC can be increased by connecting 2 memory ICs in such a way that their :

The key's answer is Data bus is in series and address bus in parallel.To widen the word, both chips must respond to the same address, so their address lines (and chip selects) are connected in common, in parallel. Their data lines are not shared: one chip supplies the lower bits and the other the upper bits, placed one after the other to form a bus twice as wide, which the paper calls the data bus in series. Two 1K × 4 chips connected this way make a 1K × 8 memory.The opposite arrangement, data lines in common and the address range extended with a decoder, increases the number of words, not the word size. Connecting both buses in common would make the two chips drive the same data lines at once.

Q: The minimum memory size to implement a BCD to seven segment decoder will be :

The minimum memory size is 10 bytes, as the key states.A BCD to seven-segment decoder can be built as a look-up table in ROM. The input is a 4-bit BCD digit and the output is the seven segment lines a to g, which fit in one byte. Only the digits 0 to 9 are valid BCD, so ten locations of one byte each are enough: 10 bytes.A physical ROM with four address lines has 16 locations, so a chip would be 16 bytes (option A); the six codes 1010 to 1111 are never used in BCD, which is why the minimum is 10. 8 bytes could hold only the digits 0 to 7, and 1 k byte is far larger than needed.

Q: The write pulse width (twp) is the time for which :

The write pulse width is the time for which \(\overline{\mathrm{WR}}\) goes low.The write control line of a memory chip or peripheral is normally active low, which is why it is written with a bar. A write is performed while \(\overline{\mathrm{WR}}\) is held low, and the timing parameter \(t_{wp}\) is the minimum duration of that low pulse needed for the data to be written reliably.\(\overline{\mathrm{WR}}\) high is its inactive state, and an active-high WR is not the signal the timing diagram describes, so the other options describe the idle condition or the wrong signal.

Q: The Boolean functionA(x, y, z) = Σ(0, 3, 4, 6)B(x, y, z) = Σ(0, 1, 4, 7)C(x, y, z) = Σ(1, 5)D(x, y, z) = Σ(0, 1, 3, 5, 7)can be implemented using a :

The functions can be implemented with an 8 × 4 ROM.Each of the four functions depends on the same three variables x, y and z. Three address inputs select one of\[ 2^{3} = 8 \ \text{words} \]and each word must hold one output bit for each function, A, B, C and D, so the word length is 4 bits. The ROM size is therefore 8 words of 4 bits.An 8 × 2 ROM has too few outputs. A 4 × 4 ROM has only two address lines, too few for three variables, and a 16 × 2 ROM has an unneeded fourth address line and still only two outputs.

Which of the following devices can be erased even if it is mounted on the computer motherboard?

A.EEPROM
B.ROM
C.PROM
D.EPROM

Exam Year(s)

DSSSB AE - 2023,

Answer: A

EEPROM (electrically erasable programmable read only memory) can be erased by an electrical signal, so it can be erased and rewritten in the circuit, while it is mounted on the motherboard. EPROM needs ultraviolet light through a quartz window, so it must be taken out of the board and put under a UV lamp. ROM is programmed at manufacture and cannot be erased, and PROM can be programmed once only by the user. The answer is EEPROM, option A.

Discuss in Forum

Address and Data lines required to access 32 kB, byte organised memory will be :

A.12 and 8
B.13 and 8
C.32 and 1
D.15 and 8

Exam Year(s)

MH SET - 2019, SET Exam - 2019,

Answer: D

The memory needs 15 address lines and 8 data lines.

A byte-organised memory stores one 8-bit byte at each address, so it needs 8 data lines. The number of address lines n must satisfy \(2^{n} = \) number of locations:

\[ \begin{aligned} 32\ \text{kB} &= 32 \times 1024 \\ &= 2^{5} \times 2^{10} = 2^{15} \end{aligned} \]

so 15 address lines are needed. 12 and 13 address lines would reach only 4 kB and 8 kB, and '32 and 1' confuses the capacity with the number of lines.

Discuss in Forum

The minimum time required for memory device to put valid data on the data bus after CS goes low is called :

A.tACS : Chip select access time
B.tHZ : Chip deselection to output in tri-state
C.tLZ : Chip selection to output in tri-state
D.tAA : Address access time

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: A

The answer is tACS : Chip select access time.

In memory timing, tACS is measured from the moment chip select (CS) goes active (low) to the moment valid data appears on the data bus. It is the minimum time the processor must wait after selecting the chip before it can read.

tAA (address access time) is measured from a stable address, not from CS. tLZ is the time from chip select until the outputs leave the high-impedance state (they are driven but not yet valid), and tHZ is the time for the outputs to return to tri-state after deselection.

Discuss in Forum

An amount of memory required to store a 256 gray shade monochrome image with 512 × 512 resolution will be :

A.256 K bytes
B.512 K bytes
C.1 M bytes
D.64 K bytes

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: A

The memory needed is 256 K bytes.

256 grey shades need 8 bits per pixel, since \(2^{8} = 256\), which is one byte per pixel.

\[ \begin{aligned} 512 \times 512 &= 262144 \text{ pixels} \\ &= 262144 \text{ bytes} \\ &= 256 \times 1024 = 256\ \text{K bytes} \end{aligned} \]

512 K bytes would mean 16 bits per pixel, 1 M byte 32 bits, and 64 K bytes only 2 bits per pixel (4 grey levels).

Discuss in Forum

Match the List I with List II and select the correct answer using the codes given below it :

List I	List II
(a) SRAM	(1) Floating gate MOSFET
(b) DRAM	(2) Flip-Flop
(c) Flash Memory	(3) Magnetic
(d) Hard Disk	(4) MOSFET

Codes : (a) (b) (c) (d)

A.(1) (2) (3) (4)
B.(2) (4) (3) (1)
C.(2) (4) (1) (3)
D.(4) (1) (2) (3)

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: C

The correct code is (2) (4) (1) (3).

(a) SRAM stores each bit in a flip-flop (a latch of cross-coupled transistors).
(b) DRAM stores each bit as charge on a capacitor accessed through a MOSFET.
(c) Flash memory stores charge on the floating gate of a floating-gate MOSFET.
(d) A hard disk stores data magnetically.

Option B gives flash memory the magnetic storage of the hard disk, and options A and D misplace SRAM and DRAM.

Discuss in Forum

The word size of memory IC can be increased by connecting 2 memory ICs in such a way that their :

A.Data bus is in series and address bus in parallel
B.Data bus is in parallel and address bus in parallel
C.Data bus is in series and address bus in series
D.Data bus is in parallel and address bus in series

Exam Year(s)

MH SET - 2021, SET Exam - 2021,

Answer: A

The key's answer is Data bus is in series and address bus in parallel.

To widen the word, both chips must respond to the same address, so their address lines (and chip selects) are connected in common, in parallel. Their data lines are not shared: one chip supplies the lower bits and the other the upper bits, placed one after the other to form a bus twice as wide, which the paper calls the data bus in series. Two 1K × 4 chips connected this way make a 1K × 8 memory.

The opposite arrangement, data lines in common and the address range extended with a decoder, increases the number of words, not the word size. Connecting both buses in common would make the two chips drive the same data lines at once.

Discuss in Forum

The minimum memory size to implement a BCD to seven segment decoder will be :

A.16 bytes
B.10 bytes
C.1 k bytes
D.8 bytes

Exam Year(s)

MH SET - 2021, SET Exam - 2021,

Answer: B

The minimum memory size is 10 bytes, as the key states.

A BCD to seven-segment decoder can be built as a look-up table in ROM. The input is a 4-bit BCD digit and the output is the seven segment lines a to g, which fit in one byte. Only the digits 0 to 9 are valid BCD, so ten locations of one byte each are enough: 10 bytes.

A physical ROM with four address lines has 16 locations, so a chip would be 16 bytes (option A); the six codes 1010 to 1111 are never used in BCD, which is why the minimum is 10. 8 bytes could hold only the digits 0 to 7, and 1 k byte is far larger than needed.

Discuss in Forum

The write pulse width (t_wp) is the time for which :

A.\(\overline{\mathrm{WR}}\) goes high
B.\(\overline{\mathrm{WR}}\) goes low
C.WR goes high
D.WR goes low

Exam Year(s)

MH SET - 2023, SET Exam - 2023,

Answer: B

The write pulse width is the time for which \(\overline{\mathrm{WR}}\) goes low.

The write control line of a memory chip or peripheral is normally active low, which is why it is written with a bar. A write is performed while \(\overline{\mathrm{WR}}\) is held low, and the timing parameter \(t_{wp}\) is the minimum duration of that low pulse needed for the data to be written reliably.

\(\overline{\mathrm{WR}}\) high is its inactive state, and an active-high WR is not the signal the timing diagram describes, so the other options describe the idle condition or the wrong signal.

Discuss in Forum

The Boolean function

A(x, y, z) = Σ(0, 3, 4, 6)
B(x, y, z) = Σ(0, 1, 4, 7)
C(x, y, z) = Σ(1, 5)
D(x, y, z) = Σ(0, 1, 3, 5, 7)

can be implemented using a :

A.4 × 4 ROM
B.8 × 2 ROM
C.16 × 2 ROM
D.8 × 4 ROM

Exam Year(s)

MH SET - 2023, SET Exam - 2023,

Answer: D

The functions can be implemented with an 8 × 4 ROM.

Each of the four functions depends on the same three variables x, y and z. Three address inputs select one of

\[ 2^{3} = 8 \ \text{words} \]

and each word must hold one output bit for each function, A, B, C and D, so the word length is 4 bits. The ROM size is therefore 8 words of 4 bits.

An 8 × 2 ROM has too few outputs. A 4 × 4 ROM has only two address lines, too few for three variables, and a 16 × 2 ROM has an unneeded fourth address line and still only two outputs.

Discuss in Forum

Loading…

Topics

Other Subjects

Tags: Memory Devices Questions and Answers || Memory Devices MCQ Questions and Answers || Memory Devices GK Questions and Answers || Memory Devices GK MCQ Questions || Memory Devices Multiple Choice Questions and Answers || Memory Devices GK || GK on Memory Devices || Digital Electronics Questions and Answers || Digital Electronics MCQ Questions and Answers || Digital Electronics GK Questions and Answers || GK on Digital Electronics

Memory Devices Questions and Answers

Topics

Other Subjects

About Us

Stay informed about all important Dates & Notifications