Delay and Power Estimation Questions and Answers

Q: For CMOS circuits which of the following is true ?

The true statement is that the dynamic power consumption increases with increasing frequency of operation.A CMOS gate draws almost no current in either steady state, because one of its two transistors is always off. Power is consumed mainly when it switches, in charging and discharging the load capacitance: \(P = C V_{DD}^{2} f\). Dynamic power is therefore proportional to the switching frequency.That makes the other statements false: power during fast switching is not low, static power is very small rather than high, and dynamic power is the main consumption, not negligible.

Q: Match List I with List II and select the correct answer using the codes given below :List IList II(a) Very low static power consumption(i) Scaling(b) Image data storage(ii) Stick diagram(c) Reducing device dimensions(iii) CMOS(d) Planning of layout(iv) CCD

The correct code is (a)-(iii), (b)-(iv), (c)-(i), (d)-(ii).Very low static power consumption is the hallmark of CMOS (iii). Image data storage is done by charge-coupled devices, which hold and shift packets of charge from each pixel (iv). Reducing device dimensions is scaling (i), which shrinks transistors by a factor to raise density and speed. Planning a layout is done with stick diagrams (ii), which show the layers and connections with coloured lines before the full layout is drawn.The other codes give scaling to power consumption or the stick diagram to image storage.

Q: Which factor does not affect CMOS loading ?

The factor that does not affect CMOS loading is the output capacitance of the load gate.When a CMOS gate drives other gates, the load it sees is the input capacitance of the gates it drives, plus wiring. The driving gate charges this capacitance through its pull-up transistor and discharges it through its pull-down transistor, so the charging and discharging times set by its output resistance decide how fast it can switch.The output capacitance of the load gate sits on that gate's own output node, which the driving gate never charges, so it plays no part in loading the driver.

Q: The gate delay is proportional to :

The gate delay is proportional to Ron.Cg.A logic gate's delay is the time its driving transistor takes to charge or discharge the capacitance on its output node. The transistor in its on state acts as a resistance \(R_{on}\), and the load is mainly the gate capacitance \(C_{g}\) of the next stage's inputs. The output therefore changes like an RC circuit, with time constant\[ \tau = R_{on} C_{g} \]This is the basis of the standard estimate of inverter delay in Pucknell and Eshraghian's VLSI text, where a stage delay is expressed in units of \(\tau\).Source resistance, drain resistance and drain-substrate or gate-source capacitances alone are not the controlling terms, and \(C_{ox}\) is capacitance per unit area, not the load capacitance of the node.

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The World’s first microprocessor, 4004, was introduced by Intel in 1968. It was a 4 bit processor, but later it has introduced a new processor almost every year, like 8080, 8085, 8086, 8031 and 8051. Only 8086 processor handles 16 bit data and a micro computer was developed based on this processor. Intel also introduced 80186, 80286, 80386, 80486 and made possible to get mini computers and personal computers.

Other companies like Texas instruments, Motorola, Zilog and Analog devices have specialized in signal processing processors, communication oriented processors, better architectural processor, and discrete signal processing devices.

All the advancements mentioned above are made possible because of continuous upgradation of VLSI technology. Some of the features like cache, pipelining and branch prediction have contributed for improving performance parameters, like execution speed, large memory, fast data transfers and reduction in number of instructions. A transformation has been seen from CISC to RISC.

Identification of application and its potential for marketing provides the opportunity to companies to produce ASICs sometimes. Digital Signal Processors are employed for processing streamed data of either voice or video data.

Which one is not enhanced feature inspite of VLSI advances ?

A.Pipelining
B.Branch prediction
C.Power consumption
D.Cache

Exam Year(s)

UGC NET - 2012,

Answer: C

The passage lists cache, pipelining and branch prediction as features that improved performance, speed, memory and data transfer. Power consumption is not an enhanced feature of that kind, since it is a cost and not an improvement, and it is not listed among the advances. So pipelining, branch prediction and cache are enhanced features and power consumption is the odd one out. The answer is power consumption.

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For CMOS circuits which of the following is true ?

A.There is low power consumption during high speed switching
B.There is high power consumption in static condition
C.There is negligible power consumption during dynamic condition
D.The dynamic power consumption increases with increasing frequency of operation

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: D

The true statement is that the dynamic power consumption increases with increasing frequency of operation.

A CMOS gate draws almost no current in either steady state, because one of its two transistors is always off. Power is consumed mainly when it switches, in charging and discharging the load capacitance: \(P = C V_{DD}^{2} f\). Dynamic power is therefore proportional to the switching frequency.

That makes the other statements false: power during fast switching is not low, static power is very small rather than high, and dynamic power is the main consumption, not negligible.

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Assertion (A) : CMOS inverter is more power efficient compared to regular resistor-MOSFET inverter.
Reason (R) : The dynamic power consumption of a CMOS inverter increases with increasing switching frequency.

A.Both (A) and (R) are true and (R) is the correct explanation of (A)
B.Both (A) and (R) are true but (R) is not the correct explanation of (A)
C.(A) is true but (R) is false
D.(A) and (R) both are false

Exam Year(s)

MH SET - 2021, SET Exam - 2021,

Answer: B

Both (A) and (R) are true but (R) is not the correct explanation of (A).

The assertion is true. In a resistor-load inverter, current flows from supply to ground through the resistor whenever the output is LOW, so it wastes static power. In a CMOS inverter one of the two transistors is always off in either steady state, so almost no static current flows.

The reason is also true: dynamic power is \(P = C V_{DD}^{2} f\), rising with switching frequency. But that describes how CMOS power grows, not why CMOS is more efficient than a resistor-load inverter; the efficiency comes from the absence of static current.

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Match List I with List II and select the correct answer using the codes given below :

List I	List II
(a) Very low static power consumption	(i) Scaling
(b) Image data storage	(ii) Stick diagram
(c) Reducing device dimensions	(iii) CMOS
(d) Planning of layout	(iv) CCD

A.(a)-(i), (b)-(iii), (c)-(ii), (d)-(iv)
B.(a)-(iv), (b)-(ii), (c)-(i), (d)-(iii)
C.(a)-(i), (b)-(iv), (c)-(ii), (d)-(iii)
D.(a)-(iii), (b)-(iv), (c)-(i), (d)-(ii)

Exam Year(s)

MH SET - 2021, SET Exam - 2021,

Answer: D

The correct code is (a)-(iii), (b)-(iv), (c)-(i), (d)-(ii).

Very low static power consumption is the hallmark of CMOS (iii). Image data storage is done by charge-coupled devices, which hold and shift packets of charge from each pixel (iv). Reducing device dimensions is scaling (i), which shrinks transistors by a factor to raise density and speed. Planning a layout is done with stick diagrams (ii), which show the layers and connections with coloured lines before the full layout is drawn.

The other codes give scaling to power consumption or the stick diagram to image storage.

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Which factor does not affect CMOS loading ?

A.Charging time associated with output resistance of driving gate
B.Discharging time associated with the output resistance of driving gate
C.Output capacitance of the load gate
D.Input capacitance of the load gate

Exam Year(s)

MH SET - 2023, SET Exam - 2023,

Answer: C

The factor that does not affect CMOS loading is the output capacitance of the load gate.

When a CMOS gate drives other gates, the load it sees is the input capacitance of the gates it drives, plus wiring. The driving gate charges this capacitance through its pull-up transistor and discharges it through its pull-down transistor, so the charging and discharging times set by its output resistance decide how fast it can switch.

The output capacitance of the load gate sits on that gate's own output node, which the driving gate never charges, so it plays no part in loading the driver.

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The gate delay is proportional to :

A.Ron.Cg
B.Rs.Cds
C.Rd.Cgs
D.Ron.Cox

Exam Year(s)

MH SET - 2024, SET Exam - 2024,

Answer: A

The gate delay is proportional to Ron.Cg.

A logic gate's delay is the time its driving transistor takes to charge or discharge the capacitance on its output node. The transistor in its on state acts as a resistance \(R_{on}\), and the load is mainly the gate capacitance \(C_{g}\) of the next stage's inputs. The output therefore changes like an RC circuit, with time constant

\[ \tau = R_{on} C_{g} \]

This is the basis of the standard estimate of inverter delay in Pucknell and Eshraghian's VLSI text, where a stage delay is expressed in units of \(\tau\).

Source resistance, drain resistance and drain-substrate or gate-source capacitances alone are not the controlling terms, and \(C_{ox}\) is capacitance per unit area, not the load capacitance of the node.

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Delay and Power Estimation Questions and Answers

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