Match List I with List II and select the correct answer using codes given below.List IList II(a) Ion Implantor(i) Photolithography(b) CVD Reactor(ii) Conductor and directric film deposition(c) UV Exposure(iii) Bonding(d) Pad to pin connection(iv) Doping

The correct matching is a-iv, b-ii, c-i, d-iii.An ion implanter accelerates dopant ions into the wafer, so it is used for doping (iv).A CVD reactor deposits thin films, conducting and dielectric (printed 'directric'), from gas-phase reactions (ii).UV exposure transfers the mask pattern to photoresist in photolithography (i).Pad to pin connection is made by wire bonding (iii).The other codes send UV exposure to film deposition or the ion implanter to photolithography, which mixes up the patterning step with the doping and deposition steps it prepares for.

Match List-I with List-II :List-IList-II(a) Gate conductor(i) SiO2 layer(b) Masking impurity diffusion(ii) Polysilicon(c) Isolation method(iii) Stick diagram(d) Layout planning(iv) Trench oxidation (LOCOS)

The correct matching is a-ii, b-i, c-iv, d-iii.(a) The gate conductor of MOS transistors is usually doped polysilicon (ii).(b) A patterned SiO2 layer masks the silicon against impurity diffusion (i).(c) Devices are isolated by local oxidation of silicon (LOCOS) or trench isolation (iv).(d) Layout is planned with stick diagrams, which show the layers and their connections before exact geometry is drawn (iii).The other codes place the oxide mask, the stick diagram or the isolation method against the wrong item.

Match List I with List II :List IList II(a) Si + O2(1) Wet oxidation(b) Si + 2H2O(2) Operates for only few seconds at high temperatures(c) Ion implantation(3) Dry oxidation(d) Rapid thermal processing(4) Projected rangeCodes : (a) (b) (c) (d)

The correct code is (3) (1) (4) (2).(a) Si + O2 → SiO2 uses dry oxygen: dry oxidation.(b) Si + 2H2O → SiO2 + 2H2 uses steam: wet oxidation.(c) In ion implantation the mean depth the ions reach is called the projected range.(d) Rapid thermal processing heats the wafer to high temperature for only a few seconds.Options B and D swap dry and wet oxidation, and option A gives ion implantation the few-seconds heating that belongs to rapid thermal processing.

CMOS Fabrication Process Questions and Answers

Q: The process of selectively removing certain protective regions from the surface of a substrate is known as :

The process is lithography.In integrated circuit fabrication, photolithography transfers a pattern from a mask to the wafer: a photoresist layer is exposed through the mask and developed, and the uncovered regions of the protective oxide are then etched away. This selective removal of protective regions opens windows for diffusion, implantation or contacts.Epitaxy grows a new crystal layer on the substrate. Metalization deposits metal for interconnections. Bonding attaches wires from the chip to the package leads. None of these removes protective regions selectively.

Q: Thermal oxidation in IC fabrication is a process carried out at :

Thermal oxidation is carried out at high temperature.Silicon wafers are heated in a furnace, typically around 900 to 1200 °C, in dry oxygen or steam. At these temperatures oxygen diffuses through the growing oxide and reacts with silicon at the interface to form SiO2 layers used as masks, gate oxides and insulation.At room temperature silicon only forms a native oxide a few nanometres thick, and sub-zero temperatures would stop the reaction altogether. Low pressure is a feature of LPCVD deposition, not of thermal oxidation, which is usually run at atmospheric pressure.

Q: The technique of growing an oriented single crystal layer on a substrate wafer is called :

The technique is epitaxy.Epitaxy (Greek epi, upon, and taxis, arrangement) is the growth of a thin single-crystal layer on a single-crystal substrate so that the layer continues the substrate's crystal orientation. Vapour phase epitaxy, for example, deposits silicon from silane or silicon tetrachloride onto a heated wafer, and the layer's doping can be set independently of the substrate.Oxidation grows an amorphous SiO2 layer, ion implantation and diffusion introduce dopants into the existing crystal; none of them grows a new oriented crystal layer.

Q: ASSERTION (A) : Epitaxy refers to the deposition of a crystalline overlayer on a crystalline substrate.REASON (R) : An epitaxial layer cannot be doped during growth phase.

The answer is (A) is true but (R) is false.The Assertion is the standard definition: epitaxy is the deposition of a crystalline overlayer on a crystalline substrate, the layer following the substrate's crystal structure and orientation.The Reason is false. One of the main advantages of epitaxy is that the layer can be doped during growth, by adding a dopant gas such as phosphine (PH3), arsine or diborane to the reactor. This in-situ doping lets a lightly doped layer be grown on a heavily doped substrate, as for the collector of a bipolar transistor.

Q: Hydrofluoric acid is preferred in wet etching. Which of the following is/are correct for Hydrofluoric acid (HF) ?(1) HF does not attack SiO2(2) HF attacks SiO2(3) HF affects silicon substrate underneath(4) HF does not affect silicon substrate underneath

The correct statements are 2 and 4.Hydrofluoric acid etches silicon dioxide readily, through the reaction SiO2 + 6HF → H2SiF6 + 2H2O, so statement 2 is correct. It hardly attacks the silicon underneath, which makes it highly selective: an oxide layer can be removed without damaging the substrate, so statement 4 is correct.Statement 1 contradicts statement 2, and statement 3 contradicts statement 4, so every option containing 1 or 3 is wrong. This selectivity is exactly why HF (often buffered with ammonium fluoride) is preferred for oxide wet etching.

Q: Which solution is used when the silicon water undergoes chemical-mechanical polishing ?

The solution used is a slurry of very fine SiO2 particles in a basic NaOH solution.Chemical-mechanical polishing of silicon wafers (the paper prints 'water') combines a mechanical action, the abrasion of very fine silica particles, with a chemical action, the attack of an alkaline solution on the silicon surface. Standard texts such as Sze's describe the polishing slurry as a colloidal suspension of fine SiO2 particles in an aqueous sodium hydroxide solution.A slurry of silica alone gives only the mechanical part, and NaOH alone only the chemical part, so options C and D are incomplete. The KOH option names a different base from the one the standard description gives.

Direction for [ Question No: 1 To 1 ] :

Directions : Q. Nos. 61 to 70, the following items consist of two statements, one labelled the "Assertion (A)" and the other labelled the "Reason (R)". You are to examine these two statements carefully and decide if the Assertion (A) and the Reason (R) are individually true and if so, whether the Reason (R) is a correct explanation of the Assertion (A). Select your answers to these items using the codes given below and mark your answer accordingly.

Assertion (A) : A p-channel enhancement MOSFET based transistor can be turn on prematurely.

Reason (R) : Most contaminants in MOS fabrication are mobile positively charged ions and they get trapped between the gate and the substrate in a n-channel enhancement MOSFET, whereas they are trapped on the other side of the substrate in the case of a p-channel enhancement MOSFET.

A.Both (A) and (R) are correct and (R) is correct explanation of (A).
B.Both (A) and (R) are correct, but (R) is not correct explanation of (A).
C.(A) is true, but (R) is false.
D.(A) is false, but (R) is true.

Exam Year(s)

UGC NET - 2013,

Answer: A

The key takes both statements as correct and the reason as the explanation, the first option. Mobile positive ions, such as sodium, trapped in the oxide between the gate and the substrate, add a positive charge that acts like a positive gate voltage on the channel.

In a p-channel enhancement device, which needs a negative gate voltage to turn on, this shifts the threshold so that the device can turn on prematurely, and the reason describes this contamination. So the reason explains the assertion, and the options that deny this are not the keyed answer.

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The process of selectively removing certain protective regions from the surface of a substrate is known as :

A.Epitaxy
B.Lithography
C.Metalization
D.Bonding

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: B

The process is lithography.

In integrated circuit fabrication, photolithography transfers a pattern from a mask to the wafer: a photoresist layer is exposed through the mask and developed, and the uncovered regions of the protective oxide are then etched away. This selective removal of protective regions opens windows for diffusion, implantation or contacts.

Epitaxy grows a new crystal layer on the substrate. Metalization deposits metal for interconnections. Bonding attaches wires from the chip to the package leads. None of these removes protective regions selectively.

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Thermal oxidation in IC fabrication is a process carried out at :

A.High temperature
B.Low pressure
C.Sub zero temperature
D.Room temperature

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: A

Thermal oxidation is carried out at high temperature.

Silicon wafers are heated in a furnace, typically around 900 to 1200 °C, in dry oxygen or steam. At these temperatures oxygen diffuses through the growing oxide and reacts with silicon at the interface to form SiO₂ layers used as masks, gate oxides and insulation.

At room temperature silicon only forms a native oxide a few nanometres thick, and sub-zero temperatures would stop the reaction altogether. Low pressure is a feature of LPCVD deposition, not of thermal oxidation, which is usually run at atmospheric pressure.

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Match List I with List II and select the correct answer using codes given below.

List I	List II
(a) Ion Implantor	(i) Photolithography
(b) CVD Reactor	(ii) Conductor and directric film deposition
(c) UV Exposure	(iii) Bonding
(d) Pad to pin connection	(iv) Doping

A.a-i, b-iii, c-ii, d-iv
B.a-ii, b-iv, c-i, d-iii
C.a-iv, b-ii, c-i, d-iii
D.a-iii, b-ii, c-i, d-iv

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: C

The correct matching is a-iv, b-ii, c-i, d-iii.

An ion implanter accelerates dopant ions into the wafer, so it is used for doping (iv).
A CVD reactor deposits thin films, conducting and dielectric (printed 'directric'), from gas-phase reactions (ii).
UV exposure transfers the mask pattern to photoresist in photolithography (i).
Pad to pin connection is made by wire bonding (iii).

The other codes send UV exposure to film deposition or the ion implanter to photolithography, which mixes up the patterning step with the doping and deposition steps it prepares for.

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The technique of growing an oriented single crystal layer on a substrate wafer is called :

A.Oxidation
B.Ion-implantation
C.Epitaxy
D.Diffusion

Exam Year(s)

MH SET - 2019, SET Exam - 2019,

Answer: C

The technique is epitaxy.

Epitaxy (Greek epi, upon, and taxis, arrangement) is the growth of a thin single-crystal layer on a single-crystal substrate so that the layer continues the substrate's crystal orientation. Vapour phase epitaxy, for example, deposits silicon from silane or silicon tetrachloride onto a heated wafer, and the layer's doping can be set independently of the substrate.

Oxidation grows an amorphous SiO₂ layer, ion implantation and diffusion introduce dopants into the existing crystal; none of them grows a new oriented crystal layer.

Discuss in Forum

ASSERTION (A) : Epitaxy refers to the deposition of a crystalline overlayer on a crystalline substrate.
REASON (R) : An epitaxial layer cannot be doped during growth phase.

A.Both (A) and (R) are true and (R) is correct explanation of (A)
B.Both (A) and (R) are true but (R) is not correct explanation of (A)
C.(A) is true but (R) is false
D.(A) and (R) both are false

Exam Year(s)

MH SET - 2019, SET Exam - 2019,

Answer: C

The answer is (A) is true but (R) is false.

The Assertion is the standard definition: epitaxy is the deposition of a crystalline overlayer on a crystalline substrate, the layer following the substrate's crystal structure and orientation.

The Reason is false. One of the main advantages of epitaxy is that the layer can be doped during growth, by adding a dopant gas such as phosphine (PH₃), arsine or diborane to the reactor. This in-situ doping lets a lightly doped layer be grown on a heavily doped substrate, as for the collector of a bipolar transistor.

Discuss in Forum

Match List-I with List-II :

List-I	List-II
(a) Gate conductor	(i) SiO₂ layer
(b) Masking impurity diffusion	(ii) Polysilicon
(c) Isolation method	(iii) Stick diagram
(d) Layout planning	(iv) Trench oxidation (LOCOS)

A.a-ii, b-iii, c-iv, d-i
B.a-iii, b-i, c-ii, d-iv
C.a-iv, b-i, c-ii, d-iii
D.a-ii, b-i, c-iv, d-iii

Exam Year(s)

MH SET - 2019, SET Exam - 2019,

Answer: D

The correct matching is a-ii, b-i, c-iv, d-iii.

(a) The gate conductor of MOS transistors is usually doped polysilicon (ii).
(b) A patterned SiO₂ layer masks the silicon against impurity diffusion (i).
(c) Devices are isolated by local oxidation of silicon (LOCOS) or trench isolation (iv).
(d) Layout is planned with stick diagrams, which show the layers and their connections before exact geometry is drawn (iii).

The other codes place the oxide mask, the stick diagram or the isolation method against the wrong item.

Discuss in Forum

Hydrofluoric acid is preferred in wet etching. Which of the following is/are correct for Hydrofluoric acid (HF) ?

(1) HF does not attack SiO₂
(2) HF attacks SiO₂
(3) HF affects silicon substrate underneath
(4) HF does not affect silicon substrate underneath

A.1 and 2
B.2 and 3
C.2 and 4
D.1 and 3

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: C

The correct statements are 2 and 4.

Hydrofluoric acid etches silicon dioxide readily, through the reaction SiO₂ + 6HF → H₂SiF₆ + 2H₂O, so statement 2 is correct. It hardly attacks the silicon underneath, which makes it highly selective: an oxide layer can be removed without damaging the substrate, so statement 4 is correct.

Statement 1 contradicts statement 2, and statement 3 contradicts statement 4, so every option containing 1 or 3 is wrong. This selectivity is exactly why HF (often buffered with ammonium fluoride) is preferred for oxide wet etching.

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Which solution is used when the silicon water undergoes chemical-mechanical polishing ?

A.a slurry of very fine \(\text{SiO}_{2}\) particles in basic KOH solution
B.a slurry of very fine \(\text{SiO}_{2}\) particles in a basic NaOH solution
C.a slurry of very fine \(\text{SiO}_{2}\) solution only
D.in a NaOH solution only

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: B

The solution used is a slurry of very fine SiO₂ particles in a basic NaOH solution.

Chemical-mechanical polishing of silicon wafers (the paper prints 'water') combines a mechanical action, the abrasion of very fine silica particles, with a chemical action, the attack of an alkaline solution on the silicon surface. Standard texts such as Sze's describe the polishing slurry as a colloidal suspension of fine SiO₂ particles in an aqueous sodium hydroxide solution.

A slurry of silica alone gives only the mechanical part, and NaOH alone only the chemical part, so options C and D are incomplete. The KOH option names a different base from the one the standard description gives.

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10.

Match List I with List II :

List I	List II
(a) Si + O₂	(1) Wet oxidation
(b) Si + 2H₂O	(2) Operates for only few seconds at high temperatures
(c) Ion implantation	(3) Dry oxidation
(d) Rapid thermal processing	(4) Projected range

Codes : (a) (b) (c) (d)

A.(3) (1) (2) (4)
B.(1) (3) (4) (2)
C.(3) (1) (4) (2)
D.(1) (2) (4) (3)

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: C

The correct code is (3) (1) (4) (2).

(a) Si + O₂ → SiO₂ uses dry oxygen: dry oxidation.
(b) Si + 2H₂O → SiO₂ + 2H₂ uses steam: wet oxidation.
(c) In ion implantation the mean depth the ions reach is called the projected range.
(d) Rapid thermal processing heats the wafer to high temperature for only a few seconds.

Options B and D swap dry and wet oxidation, and option A gives ion implantation the few-seconds heating that belongs to rapid thermal processing.

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CMOS Fabrication Process Questions and Answers

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