CMOS Inverter Characteristics Questions and Answers

Q: Which one of the following is not an advantage of CMOS technology over NMOS ?

The one that is not an advantage is less number of fabrication steps.CMOS needs both n-channel and p-channel transistors on the same chip, so it needs extra masks and steps to form the wells (n-well, p-well or twin-tub) in which one type sits. A CMOS process is therefore more complex than an NMOS process, not simpler.The other three are genuine advantages of CMOS: almost no static power, which allows a high density of logic on a chip without overheating, and a rail-to-rail output swing that gives high noise immunity.

Q: For an NMOS inverter the ratio of Zpu (pull up impedance) and Zpd (pull down impendance) has to be at least :

The ratio must be at least 4 : 1.In an NMOS inverter with a depletion-mode pull-up, the output low voltage depends on the ratio of the pull-up impedance to the pull-down impedance. For an inverter driven by another inverter to produce a low output well below the switching threshold, the standard design rule is\[ \frac{Z_{pu}}{Z_{pd}} \ge \frac{4}{1} \]If the inverter is driven through one or more pass transistors, the ratio rises to 8 : 1. Ratios of 2 : 1, 1 : 2 or 1 : 4 make the pull-up too strong, so the output cannot be pulled low enough.

Q: The pull up to pull down impedance ratio for an nMOS inverter driven by another nMOS inverter is .........

The ratio is 4/1.For an nMOS inverter with a depletion-mode pull-up, the pull-up to pull-down impedance ratio \(Z_{pu}/Z_{pd}\) must be at least 4:1 when the inverter is driven directly by another nMOS inverter, so that its output low is low enough and its switching threshold sits near the middle of the logic swing.8/1 is the ratio needed when the inverter is driven through one or more pass transistors, because the pass transistor drops a threshold voltage and reduces the input high level. 8/3 and 1/4 are not the standard design ratios; 1/4 would invert the required relationship.

Which one of the following is not an advantage of CMOS technology over NMOS ?

A.Very low static power consumption
B.High density of logic functions on a chip
C.Less number of fabrication steps
D.High noise immunity

Exam Year(s)

MH SET - 2021, SET Exam - 2021,

Answer: C

The one that is not an advantage is less number of fabrication steps.

CMOS needs both n-channel and p-channel transistors on the same chip, so it needs extra masks and steps to form the wells (n-well, p-well or twin-tub) in which one type sits. A CMOS process is therefore more complex than an NMOS process, not simpler.

The other three are genuine advantages of CMOS: almost no static power, which allows a high density of logic on a chip without overheating, and a rail-to-rail output swing that gives high noise immunity.

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For an NMOS inverter the ratio of Zpu (pull up impedance) and Zpd (pull down impendance) has to be at least :

A.1 : 4
B.4 : 1
C.1 : 2
D.2 : 1

Exam Year(s)

MH SET - 2023, SET Exam - 2023,

Answer: B

The ratio must be at least 4 : 1.

In an NMOS inverter with a depletion-mode pull-up, the output low voltage depends on the ratio of the pull-up impedance to the pull-down impedance. For an inverter driven by another inverter to produce a low output well below the switching threshold, the standard design rule is

\[ \frac{Z_{pu}}{Z_{pd}} \ge \frac{4}{1} \]

If the inverter is driven through one or more pass transistors, the ratio rises to 8 : 1. Ratios of 2 : 1, 1 : 2 or 1 : 4 make the pull-up too strong, so the output cannot be pulled low enough.

Discuss in Forum

The pull up to pull down impedance ratio for an nMOS inverter driven by another nMOS inverter is .........

A.8/1
B.4/1
C.8/3
D.1/4

Exam Year(s)

MH SET - 2025, SET Exam - 2025,

Answer: B

The ratio is 4/1.

For an nMOS inverter with a depletion-mode pull-up, the pull-up to pull-down impedance ratio \(Z_{pu}/Z_{pd}\) must be at least 4:1 when the inverter is driven directly by another nMOS inverter, so that its output low is low enough and its switching threshold sits near the middle of the logic swing.

8/1 is the ratio needed when the inverter is driven through one or more pass transistors, because the pass transistor drops a threshold voltage and reduces the input high level. 8/3 and 1/4 are not the standard design ratios; 1/4 would invert the required relationship.

Discuss in Forum

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CMOS Inverter Characteristics Questions and Answers

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