Hardware Description Languages Questions and Answers

Q: What does the following HDL statement mean ?wire [7 : 0] data-a;

The statement declares that data-a is an 8-bit wire and the msb is bit 7.In Verilog, a vector declaration wire [msb : lsb] name; gives the range of bit indices with the left-hand number as the most significant bit. [7 : 0] covers bits 7, 6, 5, 4, 3, 2, 1 and 0, eight bits in all, with bit 7 the msb and bit 0 the lsb.Counting 7 − 0 + 1 gives 8 bits, not 4, and bit 7 is on the most significant (left) side of the range, not the least, so the other three options are wrong.

Q: Hierarchy of system design is :

The hierarchy is system level, register transfer level, logic gate level, circuit level, physical level.VLSI design proceeds top-down, from the most abstract description to the most concrete. The system level states what the chip must do; the register transfer level describes data moving between registers through functional blocks; the logic gate level implements these with gates and flip-flops; the circuit level realises each gate with transistors; and the physical level is the layout of those transistors on silicon.The other options start from the physical or gate level, or put the circuit level before register transfer, which breaks the order of abstraction.

Q: VHDL ..................... represents a component's external behavior and interface.

The VHDL entity represents a component's external behaviour and interface.A VHDL design unit has two parts. The entity declaration names the component and lists its ports (inputs, outputs and their types) and generics; it is what other designs see when they use the component, like a symbol or a pin-out. The architecture body describes what goes on inside, the internal behaviour or structure that implements the entity.A port is a single connection point listed inside the entity, not the whole interface. A signal is an internal wire within an architecture. The architecture is the implementation, the opposite of the external view the question asks about.

Q: ................... are employed to specify parameters that can be supplied to VHDL entities.

Parameters supplied to VHDL entities are specified by generics.A generic clause in an entity declaration defines constants, such as a bus width or a delay, whose values can be set when the entity is instantiated with a generic map. This lets one design, for example an N-bit adder, be reused with different sizes.Ports define the signals flowing in and out of the entity, not its parameters; 'port numbers' is not a VHDL construct. Packages hold shared declarations such as types, constants and functions for many design units. Declarations is a general term, not the mechanism for parameterising an entity.

What does the following HDL statement mean ?

wire [7 : 0] data-a;

A.data-a is an 8-bit wire and the msb is bit 7
B.data-a is a 4-bit wire and the msb is bit 7
C.data-a is a 4-bit wire and the lsb is bit 7
D.data-a is a 8-bit wire and the lsb is bit 7

Exam Year(s)

MH SET - 2019, SET Exam - 2019,

Answer: A

The statement declares that data-a is an 8-bit wire and the msb is bit 7.

In Verilog, a vector declaration wire [msb : lsb] name; gives the range of bit indices with the left-hand number as the most significant bit. [7 : 0] covers bits 7, 6, 5, 4, 3, 2, 1 and 0, eight bits in all, with bit 7 the msb and bit 0 the lsb.

Counting 7 − 0 + 1 gives 8 bits, not 4, and bit 7 is on the most significant (left) side of the range, not the least, so the other three options are wrong.

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Hierarchy of system design is :

A.System level, register transfer level, logic gate level, circuit level, physical level
B.Physical level, register transfer level, system level, logic gate level, circuit level
C.System level, circuit level, register transfer level, logic gate level, physical level
D.Logic gate level, system level, register transfer level, circuit level, physical level

Exam Year(s)

MH SET - 2023, SET Exam - 2023,

Answer: A

The hierarchy is system level, register transfer level, logic gate level, circuit level, physical level.

VLSI design proceeds top-down, from the most abstract description to the most concrete. The system level states what the chip must do; the register transfer level describes data moving between registers through functional blocks; the logic gate level implements these with gates and flip-flops; the circuit level realises each gate with transistors; and the physical level is the layout of those transistors on silicon.

The other options start from the physical or gate level, or put the circuit level before register transfer, which breaks the order of abstraction.

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VHDL ..................... represents a component's external behavior and interface.

A.Signal
B.Port
C.Entity
D.Architecture

Exam Year(s)

MH SET - 2024, SET Exam - 2024,

Answer: C

The VHDL entity represents a component's external behaviour and interface.

A VHDL design unit has two parts. The entity declaration names the component and lists its ports (inputs, outputs and their types) and generics; it is what other designs see when they use the component, like a symbol or a pin-out. The architecture body describes what goes on inside, the internal behaviour or structure that implements the entity.

A port is a single connection point listed inside the entity, not the whole interface. A signal is an internal wire within an architecture. The architecture is the implementation, the opposite of the external view the question asks about.

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................... are employed to specify parameters that can be supplied to VHDL entities.

A.Port numbers
B.Packages
C.Declarations
D.Generics

Exam Year(s)

MH SET - 2025, SET Exam - 2025,

Answer: D

Parameters supplied to VHDL entities are specified by generics.

A generic clause in an entity declaration defines constants, such as a bus width or a delay, whose values can be set when the entity is instantiated with a generic map. This lets one design, for example an N-bit adder, be reused with different sizes.

Ports define the signals flowing in and out of the entity, not its parameters; 'port numbers' is not a VHDL construct. Packages hold shared declarations such as types, constants and functions for many design units. Declarations is a general term, not the mechanism for parameterising an entity.

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