FPGA and CPLD Architecture Questions and Answers

Q: Match the pairs and select the correct answer from the codes given below :(a) GAL(b) PAL(c) CPLD(d) FPGA(e) EEPROM(i) Complex programmable logic device(ii) Field programmable gate array logic(iii) Programmable array logic(iv) Gate array logic devices (generic)(v) Electrical erasable programmable read only memory.

The correct matching is a-iv, b-iii, c-i, d-ii, e-v.GAL is Generic Array Logic, a reprogrammable successor of the PAL (iv).PAL is Programmable Array Logic (iii).CPLD is a Complex Programmable Logic Device (i).FPGA is a Field Programmable Gate Array (ii).EEPROM is an Electrically Erasable Programmable Read Only Memory (v).Every code gets EEPROM right except one, so the choice turns on the four logic devices. The other codes swap GAL with PAL or CPLD with FPGA, which the expansions of the acronyms rule out.

Q: Reliable clock distribution is key to synchronous operation of high speed digital circuits. The device used for clock synchronisation in FPGA is :

The device is the DLL (delay-locked loop).FPGAs include delay-locked loops (and later digital clock managers built around them) to remove clock skew. A DLL compares the clock arriving at the logic with the incoming clock and inserts just enough delay to align them, so that every flip-flop on the chip sees its clock edge at the same time; it can also multiply, divide or shift the clock phase.The CLB (configurable logic block) holds the look-up tables and flip-flops, the IOB (input/output block) interfaces the pins, and JTAG is the boundary-scan test and programming interface. None of them synchronises the clock.

Q: Which one of the following is not a PLD ?

The one that is not a PLD is the CLA.CLA stands for carry look-ahead adder, a fixed arithmetic circuit that speeds up addition by computing the carries in parallel from generate and propagate signals. It cannot be programmed to perform another function.The others are programmable logic devices. A PLA has programmable AND and OR arrays; a CPLD (complex PLD) combines several PAL-like blocks with a programmable interconnect; and a PROM, including a serial PROM, is the simplest PLD, a fixed AND array (the address decoder) followed by a programmable OR array.

Q: What does SPLD stand for in the context described ?

SPLD stands for Simple Programmable Logic Device, which the keyed option gives as 'Simple Programming Logic Device'.Programmable logic is grouped by size. Simple PLDs are the small devices, PROMs, PALs, PLAs and GALs, built from a programmable AND array feeding an OR array, with perhaps a few dozen macrocells. Complex PLDs (CPLDs) combine many SPLD-like blocks on one chip with a programmable interconnect, and FPGAs go further with a large array of logic blocks and routing.The device is not inherently sequential, 'Systematic PLD' and 'Structured Programming and Logic Device' are not recognised expansions, and only the first option keeps the 'Simple ... Logic Device' that the abbreviation stands for.

Q: What is the role of the Global Clock Network in CPLD ?

The Global Clock Network synchronizes all clock signals in the device.A CPLD has dedicated global clock input pins connected through a low-skew distribution network to every macrocell's flip-flop. Because the clock arrives at all registers at almost the same instant, the whole design behaves synchronously and its timing is predictable, which is one of the main selling points of CPLDs.Configuration is done through the programming interface (JTAG and the non-volatile configuration cells), not the clock network. The clock network is central to meeting timing constraints, so it certainly has an impact on them. Like any network it consumes some power, but it is not 'used for' power consumption.

Q: What is the primary building block of a CPLD ?

The primary building block of a CPLD is the macro cell.A complex programmable logic device consists of several function blocks connected by a central programmable interconnect matrix. Each function block contains a number of macrocells, each with a programmable AND-OR array (sum of products) feeding a configurable flip-flop and output logic. The macrocell is therefore the unit in which logic is implemented.A flip-flop is only part of a macrocell. Simple gates are what the AND-OR array is made of. Block RAM is a memory resource found mainly in FPGAs, not the basic building block of a CPLD.

Match the pairs and select the correct answer from the codes given below :

(a) GAL
(b) PAL
(c) CPLD
(d) FPGA
(e) EEPROM

(i) Complex programmable logic device
(ii) Field programmable gate array logic
(iii) Programmable array logic
(iv) Gate array logic devices (generic)
(v) Electrical erasable programmable read only memory.

A.a-ii, b-i, c-iv, d-iii, e-v
B.a-i, b-ii, c-iii, d-iv, e-v
C.a-i, b-iv, c-iii, d-v, e-ii
D.a-iv, b-iii, c-i, d-ii, e-v
E.a-iii, b-iv, c-ii, d-i, e-v

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: D

The correct matching is a-iv, b-iii, c-i, d-ii, e-v.

GAL is Generic Array Logic, a reprogrammable successor of the PAL (iv).
PAL is Programmable Array Logic (iii).
CPLD is a Complex Programmable Logic Device (i).
FPGA is a Field Programmable Gate Array (ii).
EEPROM is an Electrically Erasable Programmable Read Only Memory (v).

Every code gets EEPROM right except one, so the choice turns on the four logic devices. The other codes swap GAL with PAL or CPLD with FPGA, which the expansions of the acronyms rule out.

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Reliable clock distribution is key to synchronous operation of high speed digital circuits. The device used for clock synchronisation in FPGA is :

A.DLL
B.CLB
C.IOB
D.JTAG

Exam Year(s)

MH SET - 2021, SET Exam - 2021,

Answer: A

The device is the DLL (delay-locked loop).

FPGAs include delay-locked loops (and later digital clock managers built around them) to remove clock skew. A DLL compares the clock arriving at the logic with the incoming clock and inserts just enough delay to align them, so that every flip-flop on the chip sees its clock edge at the same time; it can also multiply, divide or shift the clock phase.

The CLB (configurable logic block) holds the look-up tables and flip-flops, the IOB (input/output block) interfaces the pins, and JTAG is the boundary-scan test and programming interface. None of them synchronises the clock.

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Which one of the following is not a PLD ?

A.PLA
B.CPLD
C.SPROM
D.CLA

Exam Year(s)

MH SET - 2021, SET Exam - 2021,

Answer: D

The one that is not a PLD is the CLA.

CLA stands for carry look-ahead adder, a fixed arithmetic circuit that speeds up addition by computing the carries in parallel from generate and propagate signals. It cannot be programmed to perform another function.

The others are programmable logic devices. A PLA has programmable AND and OR arrays; a CPLD (complex PLD) combines several PAL-like blocks with a programmable interconnect; and a PROM, including a serial PROM, is the simplest PLD, a fixed AND array (the address decoder) followed by a programmable OR array.

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What does SPLD stand for in the context described ?

A.Simple Programming Logic Device
B.Sequential Programmable Logic Device
C.Systematic PLD
D.Structured Programming and Logic Device

Exam Year(s)

MH SET - 2024, SET Exam - 2024,

Answer: A

SPLD stands for Simple Programmable Logic Device, which the keyed option gives as 'Simple Programming Logic Device'.

Programmable logic is grouped by size. Simple PLDs are the small devices, PROMs, PALs, PLAs and GALs, built from a programmable AND array feeding an OR array, with perhaps a few dozen macrocells. Complex PLDs (CPLDs) combine many SPLD-like blocks on one chip with a programmable interconnect, and FPGAs go further with a large array of logic blocks and routing.

The device is not inherently sequential, 'Systematic PLD' and 'Structured Programming and Logic Device' are not recognised expansions, and only the first option keeps the 'Simple ... Logic Device' that the abbreviation stands for.

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Which statement accurately describes the programming of an FPGA ?

A.FPGA programming is permanent and cannot be changed.
B.FPGA programming is done using machine code
C.FPGA programming is done using hardware description languages (HDLs) or schematic entry
D.FPGA programming is only possible in a controlled laboratory environment

Exam Year(s)

MH SET - 2024, SET Exam - 2024,

Answer: C

FPGA programming is done using hardware description languages (HDLs) or schematic entry.

A designer describes the circuit in VHDL or Verilog, or draws it as a schematic. Vendor tools synthesise this into a netlist, map it onto the device's logic blocks, place and route it, and produce a configuration bitstream that is loaded into the FPGA.

Most FPGAs are SRAM-based, so they are reconfigurable as often as needed; only antifuse types are one-time programmable, so 'permanent' is wrong in general. The bitstream configures hardware rather than being machine code executed by a processor. And the devices are routinely reprogrammed in the field over JTAG or from flash memory, so no laboratory is required.

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What is the role of the Global Clock Network in CPLD ?

A.It synchronizes all clock signal in the devices
B.It is responsible for configuring the entire devices
C.It has no impact on timing constraints
D.It is used for power consumption

Exam Year(s)

MH SET - 2024, SET Exam - 2024,

Answer: A

The Global Clock Network synchronizes all clock signals in the device.

A CPLD has dedicated global clock input pins connected through a low-skew distribution network to every macrocell's flip-flop. Because the clock arrives at all registers at almost the same instant, the whole design behaves synchronously and its timing is predictable, which is one of the main selling points of CPLDs.

Configuration is done through the programming interface (JTAG and the non-volatile configuration cells), not the clock network. The clock network is central to meeting timing constraints, so it certainly has an impact on them. Like any network it consumes some power, but it is not 'used for' power consumption.

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What is the primary building block of a CPLD ?

A.Flip-flop
B.Gate
C.Block RAM
D.Macro cell

Exam Year(s)

MH SET - 2025, SET Exam - 2025,

Answer: D

The primary building block of a CPLD is the macro cell.

A complex programmable logic device consists of several function blocks connected by a central programmable interconnect matrix. Each function block contains a number of macrocells, each with a programmable AND-OR array (sum of products) feeding a configurable flip-flop and output logic. The macrocell is therefore the unit in which logic is implemented.

A flip-flop is only part of a macrocell. Simple gates are what the AND-OR array is made of. Block RAM is a memory resource found mainly in FPGAs, not the basic building block of a CPLD.

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