Logic Gates Questions and Answers

Answer: B

The expression is X = a · (b + c). Reading the diagram from the left: the third input is C-bar, which passes through a NOT gate, so the signal that leaves the NOT gate is C. That signal and B go to the OR gate, which gives (b + c). The output of the OR gate and the input A go to the AND gate, so

The option a + (b · c) would need an AND on the first stage and an OR on the last, which is the reverse of the arrangement, and (a · b) + c would put a and b together. The expression a + b + c would be a single OR gate of the three inputs. The answer is X = a · (b + c).

Answer: C

The inputs must be A = 1, B = 0 and C = 1, option (C). The circuit passes A and B to an OR gate, and the output of that gate and C go to an AND gate, so \(Y = (A + B)\cdot C\). For Y to be 1, C must be 1 and at least one of A and B must be 1. Option (A), 0, 1, 0, has C = 0, which keeps the AND gate output at 0. Option (B), 1, 0, 0, has C = 0 too. Option (D), 1, 1, 0, also has C = 0. Only option (C) has C = 1 together with a 1 at the OR gate, so it gives Y = 1.

Answer: C

The circuit gives x XOR y. The top AND gate receives x and the complement of y, and the bottom AND gate receives the complement of x and y. The OR gate combines them:

\[ F = x \cdot \bar{y} + \bar{x} \cdot y \]

This expression is the exclusive-OR, which is 1 only when x and y differ. OR and AND would not need the inverters, and XNOR is the complement, 1 when the inputs are equal.

Answer: D

Statements 1 and 3 are correct, which is option (D). A NAND gate is an AND gate followed by an inverter (AND-invert). By De Morgan's theorem, \(\overline{AB} = \bar{A} + \bar{B}\), so it is equally an OR gate with inverted inputs, which is a bubbled OR. An OR-invert gate is a NOR gate, and a bubbled AND is also a NOR, since \(\bar{A}\bar{B} = \overline{A+B}\). That excludes statements 2 and 4, and with them the options (A), (B) and (C).

Answer: D

The key accepts (i) and (iii), the fourth option. A tri-state buffer provides a high impedance state when it is off, which disconnects the output from the line so that many devices can share a bus, and the key also counts the reduction of current drawn from the shared line as a benefit.

The remaining options each carry one of (ii) or (iv), which the key does not accept, so they do not match the key's choice of the fourth option.

Answer: D

The logic function whose output is low only when both inputs are high is NAND.

A NAND gate is an AND gate followed by an inverter, so it gives 0 only for the input 1 1 and gives 1 for all the other three input combinations.

AND gives high only when both inputs are high, OR gives low only when both inputs are low, and NOR gives high only when both inputs are low.

Its truth table is 00 gives 1, 01 gives 1, 10 gives 1 and 11 gives 0. A NAND is also a universal gate, since any other gate can be built from NAND gates alone, which is why it is so common in integrated circuits.

Answer: C

The EX-OR and EX-NOR gates are best suited for parity checking and generation. The output of an EX-OR gate is 1 when the number of 1 inputs is odd, so a chain of EX-OR gates gives the parity bit of a word, and an EX-NOR gives the complementary parity.

AND, OR and NOT gates, or NAND and NOR gates, can build any function but need many more gates to do the same parity job. Option C is correct. The parity of a word is obtained by taking the EX-OR of all its bits, so a tree of such gates is used both to generate a parity bit and to check it.

Answer: B

The circuit is an XNOR gate. The first AND gate receives the inverted inputs, so it gives the value \(\bar{A}\bar{B}\), and the second AND gate gives AB. The OR gate joins them.

\[ X = \bar{A}\bar{B} + AB \]

This is 1 when the two inputs are equal, which is the truth table of XNOR. An XOR gate gives 1 when the inputs differ, and XAND and XNAND are not standard gates. Option B is correct.

Answer: B

A NAND gate is also called a bubbled OR gate, option (B). By De Morgan's theorem \(\overline{AB} = \bar{A} + \bar{B}\), so a NAND gate behaves as an OR gate with inverted (bubbled) inputs.

A bubbled AND gate (option A) would give \(\bar{A}\bar{B}\), which is the NOR function. A bubbled NOR gate (option C) gives \(\overline{\bar{A}+\bar{B}} = AB\), the AND function, and a bubbled XOR gate (option D) is not a NAND at all.

Answer: B

The correct match is IC 7410 with the triple 3-input NAND gate (iv), IC 7404 with the hex inverter (i), IC 7432 with the quad 2-input OR gate (ii) and IC 7472 with the JK master-slave flip-flop (iii), so the code is iv i ii iii, option (B).

Options A, C and D exchange some of these, for example giving the hex inverter to the 7410 or the OR gate to the 7404, which does not agree with the data sheets.