Multiplexers and Decoders Questions and Answers

Answer: D

The number of 2-input multiplexers is 1023.

A tree of 2-to-1 multiplexers halves the number of lines at each level. For \(2^{10} = 1024\) inputs the levels hold 512, 256, 128 and so on down to 1 multiplexer:

\[ \begin{aligned} N &= 512 + 256 + \dots + 2 + 1 \\ &= 2^{10} - 1 = 1023 \end{aligned} \]

In general an n-input multiplexer needs n - 1 two-input multiplexers. 9 is the number of select lines short by one (there are 10 levels), and 32 and 128 count only part of the tree.

Answer: D

A 16 : 1 multiplexer needs 4 select lines.

Each select line is a binary digit, and \(n\) select lines can address \(2^{n}\) different inputs. We need the smallest \(n\) with

\[ 2^{n} = 16 \Rightarrow n = \log_{2} 16 = 4 \]

The four lines S3 S2 S1 S0 run from 0000 to 1111 and pick inputs I0 to I15.

One select line serves a 2 : 1 MUX, two serve a 4 : 1 and three serve an 8 : 1, so 1, 2 and 3 are each too few for sixteen inputs.

Answer: C

A decoder converts \(n\) inputs to \(2^{n}\) outputs.

An \(n\)-bit input can take \(2^{n}\) distinct combinations, and a full binary decoder has one output line for each, with exactly one output active for any input code. A 2-to-4 decoder has 2 inputs and 4 outputs, a 3-to-8 decoder 3 inputs and 8 outputs, and a 4-to-16 decoder 4 inputs and 16 outputs.

\(n\) outputs would mean only one per input, which is not decoding. \(n^{2}\) happens to equal \(2^{n}\) at \(n = 2\) and \(n = 4\) but not in general (for \(n = 3\) it gives 9 rather than 8), and \(n^{n}\) grows far faster than the number of possible input codes.

Answer: D

Multiplexers are combinational circuits.

A combinational circuit's output depends only on its present inputs. A multiplexer simply routes one of its data inputs to the output according to the select inputs, with no memory, so it is combinational. Adders, decoders, encoders and comparators are other examples.

Shift registers, counters and flip-flops are sequential circuits: their outputs depend on stored state as well as on present inputs, and flip-flops are the memory elements from which registers and counters are built.

Answer: B

The multiplexer output is \(x + y\) (option B). Data inputs 1, 2 and 3 are tied to \(V_{CC}\) (logic 1) and input 0 is grounded (logic 0), so the output is 0 only when the select lines choose input 0, that is x = 0 and y = 0, and it is 1 for every other combination. That is the OR function.

\[ f = \overline{x}\,\overline{y}\cdot 0 + \overline{x}y\cdot 1 \]

\[ \quad + x\overline{y}\cdot 1 + xy\cdot 1 = x + y \]

Options A and C are 1 for most or all inputs, and option D, \(x\overline{y}\), is 1 for only one combination, so none of them matches the OR behaviour.

Answer: B

The key matches the multiplexer with the item that routes many data inputs to a single data output, so a matches 4, and the de-multiplexer with data selection, so b matches 3. The shift register is a sequential memory, so c matches 1, and the encoder converts a decimal number into binary, so d matches 2. The code is 4 3 1 2. The first option, 3 4 1 2, interchanges the first two pairs, which would call the multiplexer the data selection element and the de-multiplexer the many-to-one device, and the key does not accept that. The answer is 4 3 1 2, as the key has it.

Answer: A

The first multiplexer has z as its select line, with x on input 0 and the complement of y on input 1, so its output is \(\overline{z}x + z\overline{y}\). The second has y as its select line, with the first output on input 0 and x on input 1, so

\[ f = \overline{y}(x\overline{z} + \overline{y}z) + yx \]

\[ f = x\overline{y}\,\overline{z} + \overline{y}z + xy \]

\[ f = x\overline{z} + xy + \overline{y}z \]

The first two terms with x combine, since \(\overline{y}\,\overline{z} + y = \overline{z} + y\). So the output is option (A).