Field Effect Transistors Questions and Answers

Q: The voltage of a common source JFET amplifier depends upon its __________.

The voltage gain depends on both transconductance and internal load resistance.A JFET is controlled by its gate-source voltage, and its transconductance \(g_{m}\) gives the change in drain current per volt of input. That current flows through the drain load, so the output voltage is the current times the load resistance, giving a gain of about \(A_{v} = g_{m} r_{L}\), where \(r_{L}\) is the effective drain load (the drain resistor in parallel with the device's own drain resistance).Transconductance alone or load resistance alone gives only one factor of the product. The amplification factor is a device constant, the gain with an unlimited load, and does not describe a working stage with a finite load.

Q: \(I_{D}\) and \(V_{GS}\) notations in a FET denote the following parameters :

\(I_{D}\) and \(V_{GS}\) denote DC values.The standard notation uses the case of the symbol and of its subscript: an upper-case symbol with an upper-case subscript (\(I_{D}\), \(V_{GS}\)) is the quiescent DC value; lower-case with upper-case subscript (\(i_{D}\), \(v_{GS}\)) is the total instantaneous value; lower-case with lower-case subscript (\(i_{d}\), \(v_{gs}\)) is the instantaneous ac component; and upper-case with lower-case subscript (\(I_{d}\), \(V_{gs}\)) is the rms or phasor value of the ac component.So the other three options correspond to the other three combinations of letter case, not to the notation in the question.

Q: Compared to BJT, a JFET has :

Compared to a BJT, a JFET has higher input impedance and low voltage gain.The JFET's gate-source junction is reverse biased, so almost no gate current flows and the input impedance is very high, typically many megohms, against the kilohms of a BJT's forward-biased base-emitter junction.Its transconductance is much lower than a BJT's at the same current, so a JFET amplifier usually gives lower voltage gain. That rules out 'lower input impedance', 'higher voltage gain' and the option pairing high input impedance with high gain.

Q: Estimate VGS in the following circuit :(Figure: an n-channel MOSFET whose gate and drain are both connected to the 5 V supply; its source is connected to ground through a 7 K resistor, and a current of 0.3 mA flows down through that resistor.)

\(V_{GS}\) is about 2.9 V.The gate is tied to the 5 V supply, so \(V_{G} = 5\) V. The source voltage is the drop across the 7 K resistor carrying 0.3 mA.\[ \begin{aligned} V_{S} &= 0.3\ \text{mA} \times 7\ \text{k}\Omega = 2.1\ \text{V} \\ V_{GS} &= V_{G} - V_{S} = 5 - 2.1 = 2.9\ \text{V} \end{aligned} \]The other values would need different source voltages: 4.9 V a drop of only 0.1 V across the resistor, 3.5 V a drop of 1.5 V, and 1.5 V a drop of 3.5 V. None matches 0.3 mA through 7 kΩ.

Q: In, ................. device the conductivity of a layer of a semiconductor is modulated by a transverse electric field.

The device is the FET.In a field-effect transistor the current flows through a channel, a thin layer of semiconductor, and the voltage on the gate sets up an electric field across (transverse to) that channel. The field changes the number of carriers in the channel, and so its conductivity, which is how the gate controls the drain current. The name 'field effect' comes from this mechanism.A BJT is controlled by the injection of carriers across forward-biased junctions, with base current, not by a transverse field. A P-N diode and a Zener diode are two-terminal devices with no control electrode at all.

Q: What does the symbol IGSS represent in the context of a JFET ?

IGSS is the gate current when the gate-source junction is reverse-biased.In a JFET the gate-channel p-n junction is always operated in reverse bias. IGSS, the gate reverse current or gate leakage current, is the small current that flows into the gate with the drain shorted to the source and a specified reverse voltage applied between gate and source. It is typically in nanoamperes, which is why a JFET has a very high input resistance.The drain current is ID (with IDSS its value at VGS = 0). The gate-source voltage is VGS. Forward-biasing the gate junction is avoided in normal operation and is not what IGSS specifies.

Q: Which of the following is true about the FET as its advantage ?

The advantage is better thermal stability.In a FET, current is carried by majority carriers only, and their mobility falls as temperature rises, so the drain current tends to decrease with heating. This negative temperature coefficient prevents thermal runaway, which can destroy a bipolar transistor. FETs also offer very high input resistance, low noise and small size.A low input resistance is the opposite of the FET's main advantage, which is its very high input resistance, especially in MOSFETs. 'Big size, small life' is false, since FETs are compact and reliable. High output resistance is not usually listed as the FET's advantage over the BJT.

Q: The co-ordinates of the operating point (Q) for the following JFET circuit are ........

The operating point is \(V_{DS} = 15\) V, \(I_{D} = 5\) mA.The divider sets the gate voltage, and the source voltage is taken to sit at about the gate voltage (that is, \(V_{GS} \approx 0\), the approximation the options are built on):\[ \begin{aligned} V_{G} &= 30 \times \frac{1\ \text{M}\Omega}{3\ \text{M}\Omega} = 10\ \text{V} \\ I_{D} &\approx \frac{V_{G}}{R_{s}} = \frac{10\ \text{V}}{2\ \text{k}\Omega} = 5\ \text{mA} \\ V_{DS} &= 30 - 5\ \text{mA}(1 + 2)\ \text{k}\Omega = 15\ \text{V} \end{aligned} \]The other options put \(V_{DS}\) in millivolts. With 5 mA the two resistors drop only 15 V, which leaves 15 V, not 15 mV, across the transistor. Currents of 15 mA or 10 mA through the 3 kΩ of \(R_{D}\) and \(R_{s}\) would need 45 V or 30 V, more than or all of the supply, and are inconsistent with a 10 V gate.

Q: The drain current in a JFET is controlled by

The drain current in a JFET is controlled by the gate-source voltage.The JFET is a voltage-controlled device. A reverse bias on the gate-source junction widens the depletion region into the channel, narrowing it and reducing the drain current. Shockley's equation gives the relation:\[ I_D = I_{DSS}\left(1 - \frac{V_{GS}}{V_P}\right)^{2} \]The gate is reverse biased, so gate current is almost zero and controls nothing. In saturation the drain voltage has little effect on the current. Source current is simply the drain current flowing out, a result rather than a control.

111.

The voltage of a common source JFET amplifier depends upon its __________.

A.both transconductance and internal load resistance
B.transconductance
C.amplification factor
D.internal load resistance

Exam Year(s)

RSMSSB JE - 2025, RSMSSB - 2025,

Answer: A

The voltage gain depends on both transconductance and internal load resistance.

A JFET is controlled by its gate-source voltage, and its transconductance \(g_{m}\) gives the change in drain current per volt of input. That current flows through the drain load, so the output voltage is the current times the load resistance, giving a gain of about \(A_{v} = g_{m} r_{L}\), where \(r_{L}\) is the effective drain load (the drain resistor in parallel with the device's own drain resistance).

Transconductance alone or load resistance alone gives only one factor of the product. The amplification factor is a device constant, the gain with an unlimited load, and does not describe a working stage with a finite load.

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112.

\(I_{D}\) and \(V_{GS}\) notations in a FET denote the following parameters :

A.Total instantaneous values
B.Instantaneous ac values
C.Phasor values
D.DC values

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: D

\(I_{D}\) and \(V_{GS}\) denote DC values.

The standard notation uses the case of the symbol and of its subscript: an upper-case symbol with an upper-case subscript (\(I_{D}\), \(V_{GS}\)) is the quiescent DC value; lower-case with upper-case subscript (\(i_{D}\), \(v_{GS}\)) is the total instantaneous value; lower-case with lower-case subscript (\(i_{d}\), \(v_{gs}\)) is the instantaneous ac component; and upper-case with lower-case subscript (\(I_{d}\), \(V_{gs}\)) is the rms or phasor value of the ac component.

So the other three options correspond to the other three combinations of letter case, not to the notation in the question.

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113.

Compared to BJT, a JFET has :

A.Lower input impedance
B.Higher voltage gain
C.Higher input impedance and high voltage gain
D.Higher input impedance and low voltage gain

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: D

Compared to a BJT, a JFET has higher input impedance and low voltage gain.

The JFET's gate-source junction is reverse biased, so almost no gate current flows and the input impedance is very high, typically many megohms, against the kilohms of a BJT's forward-biased base-emitter junction.

Its transconductance is much lower than a BJT's at the same current, so a JFET amplifier usually gives lower voltage gain. That rules out 'lower input impedance', 'higher voltage gain' and the option pairing high input impedance with high gain.

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114.

Estimate V_GS in the following circuit :

(Figure: an n-channel MOSFET whose gate and drain are both connected to the 5 V supply; its source is connected to ground through a 7 K resistor, and a current of 0.3 mA flows down through that resistor.)

A.1.5 V
B.4.9 V
C.3.5 V
D.2.9 V

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: D

\(V_{GS}\) is about 2.9 V.

The gate is tied to the 5 V supply, so \(V_{G} = 5\) V. The source voltage is the drop across the 7 K resistor carrying 0.3 mA.

\[ \begin{aligned} V_{S} &= 0.3\ \text{mA} \times 7\ \text{k}\Omega = 2.1\ \text{V} \\ V_{GS} &= V_{G} - V_{S} = 5 - 2.1 = 2.9\ \text{V} \end{aligned} \]

The other values would need different source voltages: 4.9 V a drop of only 0.1 V across the resistor, 3.5 V a drop of 1.5 V, and 1.5 V a drop of 3.5 V. None matches 0.3 mA through 7 kΩ.

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115.

In, ................. device the conductivity of a layer of a semiconductor is modulated by a transverse electric field.

A.BJT
B.P-N diode
C.Zener diode
D.FET

Exam Year(s)

MH SET - 2023, SET Exam - 2023,

Answer: D

The device is the FET.

In a field-effect transistor the current flows through a channel, a thin layer of semiconductor, and the voltage on the gate sets up an electric field across (transverse to) that channel. The field changes the number of carriers in the channel, and so its conductivity, which is how the gate controls the drain current. The name 'field effect' comes from this mechanism.

A BJT is controlled by the injection of carriers across forward-biased junctions, with base current, not by a transverse field. A P-N diode and a Zener diode are two-terminal devices with no control electrode at all.

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116.

What does the symbol I_GSS represent in the context of a JFET ?

A.Drain current
B.Gate-source voltage
C.Gate current when the gate-source junction is forward-biased
D.Gate current when the gate-source junction is reverse-biased

Exam Year(s)

MH SET - 2025, SET Exam - 2025,

Answer: D

I_GSS is the gate current when the gate-source junction is reverse-biased.

In a JFET the gate-channel p-n junction is always operated in reverse bias. I_GSS, the gate reverse current or gate leakage current, is the small current that flows into the gate with the drain shorted to the source and a specified reverse voltage applied between gate and source. It is typically in nanoamperes, which is why a JFET has a very high input resistance.

The drain current is I_D (with I_DSS its value at V_GS = 0). The gate-source voltage is V_GS. Forward-biasing the gate junction is avoided in normal operation and is not what I_GSS specifies.

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117.

Which of the following is true about the FET as its advantage ?

A.Low input resistance
B.High output resistance
C.Big size, small life
D.Better thermal stability

Exam Year(s)

MH SET - 2025, SET Exam - 2025,

Answer: D

The advantage is better thermal stability.

In a FET, current is carried by majority carriers only, and their mobility falls as temperature rises, so the drain current tends to decrease with heating. This negative temperature coefficient prevents thermal runaway, which can destroy a bipolar transistor. FETs also offer very high input resistance, low noise and small size.

A low input resistance is the opposite of the FET's main advantage, which is its very high input resistance, especially in MOSFETs. 'Big size, small life' is false, since FETs are compact and reliable. High output resistance is not usually listed as the FET's advantage over the BJT.

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118.

The co-ordinates of the operating point (Q) for the following JFET circuit are ........

JFET circuit: VDD = +30 V; R1 = 2 megohm from VDD to the gate and R2 = 1 megohm from the gate to ground; drain to VDD through RD = 1 kilohm; source to ground through Rs = 2 kilohm

A.\(V_{DS}\) = 15 mV, \(I_{D}\) = 5 mA.
B.\(V_{DS}\) = 5 mV, \(I_{D}\) = 15 mA.
C.\(V_{DS}\) = 30 mV, \(I_{D}\) = 10 mA.
D.\(V_{DS}\) = 15 V, \(I_{D}\) = 5 mA.

Exam Year(s)

MH SET - 2025, SET Exam - 2025,

Answer: D

The operating point is \(V_{DS} = 15\) V, \(I_{D} = 5\) mA.

The divider sets the gate voltage, and the source voltage is taken to sit at about the gate voltage (that is, \(V_{GS} \approx 0\), the approximation the options are built on):

\[ \begin{aligned} V_{G} &= 30 \times \frac{1\ \text{M}\Omega}{3\ \text{M}\Omega} = 10\ \text{V} \\ I_{D} &\approx \frac{V_{G}}{R_{s}} = \frac{10\ \text{V}}{2\ \text{k}\Omega} = 5\ \text{mA} \\ V_{DS} &= 30 - 5\ \text{mA}(1 + 2)\ \text{k}\Omega = 15\ \text{V} \end{aligned} \]

The other options put \(V_{DS}\) in millivolts. With 5 mA the two resistors drop only 15 V, which leaves 15 V, not 15 mV, across the transistor. Currents of 15 mA or 10 mA through the 3 kΩ of \(R_{D}\) and \(R_{s}\) would need 45 V or 30 V, more than or all of the supply, and are inconsistent with a 10 V gate.

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119.

The drain current in a JFET is controlled by

A.Drain voltage
B.Gate-source voltage
C.Source current
D.Gate current

Exam Year(s)

Tripura Public Service Commission - 2026,

Answer: B

The drain current in a JFET is controlled by the gate-source voltage.

The JFET is a voltage-controlled device. A reverse bias on the gate-source junction widens the depletion region into the channel, narrowing it and reducing the drain current. Shockley's equation gives the relation:

\[ I_D = I_{DSS}\left(1 - \frac{V_{GS}}{V_P}\right)^{2} \]

The gate is reverse biased, so gate current is almost zero and controls nothing. In saturation the drain voltage has little effect on the current. Source current is simply the drain current flowing out, a result rather than a control.

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120.

For a JFET \(I_{DSS}\) = 8 mA and peak voltage \(V_p\) = -8 V, what will be the drain current for gate to source voltage of -2 V ?

A.4.5 mA
B.8 mA
C.16 mA
D.12 mA

Exam Year(s)

UGC NET - 2012,

Answer: A

The drain current is 4.5 mA (option A), from the JFET square-law relation in the saturation region.

\[ I_D = I_{DSS}\left(1 - \frac{V_{GS}}{V_p}\right)^2 \]

\[ I_D = 8\left(1 - \frac{-2}{-8}\right)^2 \]

\[ I_D = 8(0.75)^2 = 4.5\ \text{mA} \]

The value 8 mA (B) is the current at \(V_{GS} = 0\), where the bracket is 1. The values 16 mA and 12 mA are larger than \(I_{DSS}\), which a JFET cannot exceed at a gate voltage that reverse biases the channel.

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