Memory Hierarchy Questions and Answers

Q: A 4 kilobyte (KB) byte-addressable memory is realized using four 1 KB memory blocks. Two input address lines (IA4 and IA3) are connected to the chip select (CS) port of these memory blocks through a decoder as shown in the figure. The remaining ten input address lines from IA11-IA0 are connected to the address port of these blocks. The chip select (CS) is active high.The input memory addresses (IA11-IA0), in decimal, for the starting locations (Addr=0) of each block (indicated as X1, X2, X3, X4 in the figure) are among the options given below. Which one of the following options is CORRECT?

The starting addresses are (0, 8, 16, 24).Each block is selected by IA4 and IA3 through the decoder: IA4 IA3 = 00 enables X1, 01 enables X2, 10 enables X3 and 11 enables X4. The other ten lines (IA11 to IA5 and IA2 to IA0) form the address inside the block. The starting location of a block, Addr = 0, has all ten of those lines at 0, so only IA4 and IA3 can be 1:\[ \begin{aligned} X1&: 0,\quad X2: 2^{3} = 8 \\ X3&: 2^{4} = 16,\quad X4: 2^{4} + 2^{3} = 24 \end{aligned} \](0, 1024, 2048, 3072) is what the usual design gives, with the two top lines IA11 and IA10 on the decoder; here the decoder sits on bits 4 and 3. (0, 1, 2, 3) would need IA1 and IA0 on the decoder. The four blocks cannot all start at address 0, because each address enables exactly one block.

Q: The speed of information being transferred in and out of memory depends on which of the following parameters ?(i) Access time \(t_{\mathrm{A}}\)(ii) Cycle time \(t_{c}\)(iii) Access rate \(r_{\mathrm{A}}\)(iv) Bandwidth \(r_{c}\)

The key is (i) and (ii), access time and cycle time, and it rests on how the question reads the list.Memory speed is set by two times: the access time \(t_{\mathrm{A}}\), from a request to the data being available, and the cycle time \(t_{c}\), the minimum gap between two successive operations. The access rate \(r_{\mathrm{A}}\) and the bandwidth \(r_{c}\) are the reciprocals of those two (\(r_{\mathrm{A}} = 1/t_{\mathrm{A}}\), \(r_{c} = 1/t_{c}\)), so they restate the same speed as rates rather than add a separate dependence.On that reading A is the answer, and every option that adds (iii) or (iv) is wrong. A reader who counts the rates as parameters the speed depends on could choose D, and no source found settles which the question intends, so this follows the key.

Q: Which type of memory generally enables to enhance the performance of a CPU ?

Performance is enhanced by cache memory.Cache is a small, very fast memory between the CPU and main memory. It holds copies of recently and frequently used instructions and data, so most memory accesses are served at cache speed, which cuts the average access time and keeps the CPU busy.Auxiliary memory (disks) is far slower and used for bulk storage. Virtual memory enlarges the address space using disk, which adds overhead rather than speed. Associative memory is a technique for searching by content, used inside caches and TLBs, rather than the memory level that speeds up the CPU in general.

Select the option that best describes the truthfulness of the following statements. i) RAM is a volatile memory having a limited storage capacity. ii) Secondary memory is storage other than the RAM and ROM.

A.i-True, ii-True
B.i-False, ii-True
C.i-True, ii-False
D.i-False, ii-False

Exam Year(s)

DSSSB TGT - 2023,

Answer: A

Both statements are true. RAM is volatile memory, which loses its contents when power is switched off, and it has a limited storage capacity. Secondary memory is the storage other than RAM and ROM, such as hard disks, and it keeps data permanently. Marking either statement as false would be wrong, so the first option is correct. RAM is the main working memory of the computer, and secondary memory such as a hard disk or an SSD is where files are kept when the power is off.

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A 4 kilobyte (KB) byte-addressable memory is realized using four 1 KB memory blocks. Two input address lines (IA4 and IA3) are connected to the chip select (CS) port of these memory blocks through a decoder as shown in the figure. The remaining ten input address lines from IA11-IA0 are connected to the address port of these blocks. The chip select (CS) is active high.

Lines IA11 to IA5 and IA2 to IA0 form a 10-bit bus to the Addr port of four 1KB memory blocks X1 to X4; IA4 and IA3 drive decoder inputs A1 and A0, whose outputs Q0 to Q3 drive the CS of X1 to X4

The input memory addresses (IA11-IA0), in decimal, for the starting locations (Addr=0) of each block (indicated as X1, X2, X3, X4 in the figure) are among the options given below. Which one of the following options is CORRECT?

A.(0, 1, 2, 3)
B.(0, 1024, 2048, 3072)
C.(0, 8, 16, 24)
D.(0, 0, 0, 0)

Exam Year(s)

GATE CS - 2023,

Answer: C

The starting addresses are (0, 8, 16, 24).

Each block is selected by IA4 and IA3 through the decoder: IA4 IA3 = 00 enables X1, 01 enables X2, 10 enables X3 and 11 enables X4. The other ten lines (IA11 to IA5 and IA2 to IA0) form the address inside the block. The starting location of a block, Addr = 0, has all ten of those lines at 0, so only IA4 and IA3 can be 1:

\[ \begin{aligned} X1&: 0,\quad X2: 2^{3} = 8 \\ X3&: 2^{4} = 16,\quad X4: 2^{4} + 2^{3} = 24 \end{aligned} \]

(0, 1024, 2048, 3072) is what the usual design gives, with the two top lines IA11 and IA10 on the decoder; here the decoder sits on bits 4 and 3. (0, 1, 2, 3) would need IA1 and IA0 on the decoder. The four blocks cannot all start at address 0, because each address enables exactly one block.

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Which of the following are the performance parameters of memory ?

(i) Latency
(ii) Memory Cycle Time
(iii) Transfer Rate

A.(i) and (ii)
B.(ii) and (iii)
C.(i) and (iii)
D.(i), (ii) and (iii)

Exam Year(s)

MH SET - 2019, SET Exam - 2019,

Answer: D

All three are memory performance parameters, so the answer is (i), (ii) and (iii).

William Stallings gives three performance parameters for memory: access time (latency), the time to perform a read or write; memory cycle time, the access time plus any further time before a second access can start; and transfer rate, the rate at which data can be moved into or out of the memory unit.

Each option that leaves one of them out is therefore incomplete.

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The speed of information being transferred in and out of memory depends on which of the following parameters ?

(i) Access time \(t_{\mathrm{A}}\)
(ii) Cycle time \(t_{c}\)
(iii) Access rate \(r_{\mathrm{A}}\)
(iv) Bandwidth \(r_{c}\)

A.(i) & (ii)
B.(ii) & (iii)
C.(i), (ii) & (iii)
D.(i), (ii), (iii) & (iv)

Exam Year(s)

MH SET - 2023, SET Exam - 2023,

Answer: A

The key is (i) and (ii), access time and cycle time, and it rests on how the question reads the list.

Memory speed is set by two times: the access time \(t_{\mathrm{A}}\), from a request to the data being available, and the cycle time \(t_{c}\), the minimum gap between two successive operations. The access rate \(r_{\mathrm{A}}\) and the bandwidth \(r_{c}\) are the reciprocals of those two (\(r_{\mathrm{A}} = 1/t_{\mathrm{A}}\), \(r_{c} = 1/t_{c}\)), so they restate the same speed as rates rather than add a separate dependence.

On that reading A is the answer, and every option that adds (iii) or (iv) is wrong. A reader who counts the rates as parameters the speed depends on could choose D, and no source found settles which the question intends, so this follows the key.

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Which type of memory generally enables to enhance the performance of a CPU ?

A.Auxiliary Memory
B.Associative Memory
C.Cache Memory
D.Virtual Memory

Exam Year(s)

MH SET - 2025, SET Exam - 2025,

Answer: C

Performance is enhanced by cache memory.

Cache is a small, very fast memory between the CPU and main memory. It holds copies of recently and frequently used instructions and data, so most memory accesses are served at cache speed, which cuts the average access time and keeps the CPU busy.

Auxiliary memory (disks) is far slower and used for bulk storage. Virtual memory enlarges the address space using disk, which adds overhead rather than speed. Associative memory is a technique for searching by content, used inside caches and TLBs, rather than the memory level that speeds up the CPU in general.

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