Pipelining Questions and Answers

Q: Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?

The dependence that causes a data hazard is Read-after-write.In a read-after-write (true) dependence, a later instruction reads a register that an earlier instruction writes. In a pipeline the later instruction can reach its operand-read stage before the earlier one has written its result back, so it would read a stale value unless the pipeline stalls or forwards the result.Read-after-read never causes a hazard, because reading does not change the register. Write-after-read and write-after-write are name dependences: in the standard in-order pipeline, where every instruction reads early and writes in the last stage in program order, they cannot go wrong. They become hazards only in pipelines that let instructions complete out of order, where register renaming removes them.

Q: An instruction format has the following structure:Instruction Number: Opcode destination reg, source reg-1, source reg-2Consider the following sequence of instructions to be executed in a pipelined processor:I1: DIV R3, R1, R2I2: SUB R5, R3, R4I3: ADD R3, R5, R6I4: MUL R7, R3, R8Which of the following statements is/are TRUE?

Only the first statement is true: There is a RAW dependency on R3 between I1 and I2.I1 writes R3 and I2 then reads R3, so I2 must wait for I1's result: a read-after-write (true) dependency.The other three name the wrong kind of hazard. Between I1 and I3 both instructions write R3, which is write-after-write (WAW), not WAR. Between I2 and I3, I2 reads R3 and I3 later writes it, which is write-after-read (WAR), not RAW. Between I3 and I4, I3 writes R3 and I4 reads it, which is RAW, not WAW.

Q: An 8086 microprocessor can fatch and Pre-fetch upto.......... bytes of instructions and stores them in the queue :

The 8086 can prefetch up to 6 bytes.The 8086's bus interface unit fetches instruction bytes ahead of time while the execution unit is busy and stores them in a 6-byte first-in first-out instruction queue. This overlap of fetching and executing is a simple form of pipelining.8 bytes is not the 8086 figure (its 8-bit-bus sibling, the 8088, has a 4-byte queue), and 16 and 20 bytes confuse the queue with the 16-bit data bus and the 20-bit address bus.

Q: Assume that an instruction pipeline has 5 stages without any branch prediction. Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO) with state delays as 6, 8, 6, 5 and 4 ns respectively.Consider a program with 15 instructions (I1 .... I15) where only I7 is a branch instruction and I12 is the target instruction.If the branch is taken during execution of the program then what is the time needed to complete the program ?

The program takes 144ns.A pipeline's clock must suit its slowest stage, so the cycle time is 8 ns. Because the branch I7 is taken to I12, only I1 to I7 and I12 to I15 are completed: 11 instructions.With no branch prediction, the outcome is known only when I7 reaches Execute (stage 4). The three instructions fetched after it (I8, I9, I10) are flushed, a penalty of 3 cycles.\[ \begin{aligned} \text{cycles} &= (k - 1) + n + \text{penalty} \\ &= 4 + 11 + 3 = 18 \\ \text{time} &= 18 \times 8 = 144\ \text{ns} \end{aligned} \]Running all 15 instructions without the branch would take (4 + 15) x 8 = 152 ns. 210 and 216 ns ignore pipelining, and 25 ns is a single instruction's latency without the common clock.

Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?

A.Read-after-read
B.Read-after-write
C.Write-after-read
D.Write-after-write

Exam Year(s)

GATE CS - 2026,

Answer: B

The dependence that causes a data hazard is Read-after-write.

In a read-after-write (true) dependence, a later instruction reads a register that an earlier instruction writes. In a pipeline the later instruction can reach its operand-read stage before the earlier one has written its result back, so it would read a stale value unless the pipeline stalls or forwards the result.

Read-after-read never causes a hazard, because reading does not change the register. Write-after-read and write-after-write are name dependences: in the standard in-order pipeline, where every instruction reads early and writes in the last stage in program order, they cannot go wrong. They become hazards only in pipelines that let instructions complete out of order, where register renaming removes them.

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An instruction format has the following structure:

Instruction Number: Opcode destination reg, source reg-1, source reg-2

Consider the following sequence of instructions to be executed in a pipelined processor:

I1: DIV R3, R1, R2
I2: SUB R5, R3, R4
I3: ADD R3, R5, R6
I4: MUL R7, R3, R8

Which of the following statements is/are TRUE?

A.There is a RAW dependency on R3 between I1 and I2
B.There is a WAR dependency on R3 between I1 and I3
C.There is a RAW dependency on R3 between I2 and I3
D.There is a WAW dependency on R3 between I3 and I4

Exam Year(s)

GATE CS - 2024,

Answer: A

Only the first statement is true: There is a RAW dependency on R3 between I1 and I2.

I1 writes R3 and I2 then reads R3, so I2 must wait for I1's result: a read-after-write (true) dependency.

The other three name the wrong kind of hazard. Between I1 and I3 both instructions write R3, which is write-after-write (WAW), not WAR. Between I2 and I3, I2 reads R3 and I3 later writes it, which is write-after-read (WAR), not RAW. Between I3 and I4, I3 writes R3 and I4 reads it, which is RAW, not WAW.

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An 8086 microprocessor can fatch and Pre-fetch upto.......... bytes of instructions and stores them in the queue :

A.8
B.6
C.16
D.20

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: B

The 8086 can prefetch up to 6 bytes.

The 8086's bus interface unit fetches instruction bytes ahead of time while the execution unit is busy and stores them in a 6-byte first-in first-out instruction queue. This overlap of fetching and executing is a simple form of pipelining.

8 bytes is not the 8086 figure (its 8-bit-bus sibling, the 8088, has a 4-byte queue), and 16 and 20 bytes confuse the queue with the 16-bit data bus and the 20-bit address bus.

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Assume that an instruction pipeline has 5 stages without any branch prediction. Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO) with state delays as 6, 8, 6, 5 and 4 ns respectively.

Consider a program with 15 instructions (I₁ .... I₁₅) where only I₇ is a branch instruction and I₁₂ is the target instruction.

If the branch is taken during execution of the program then what is the time needed to complete the program ?

A.210ns
B.216ns
C.25ns
D.144ns

Exam Year(s)

MH SET - 2020, SET Exam - 2020,

Answer: D

The program takes 144ns.

A pipeline's clock must suit its slowest stage, so the cycle time is 8 ns. Because the branch I7 is taken to I12, only I1 to I7 and I12 to I15 are completed: 11 instructions.

With no branch prediction, the outcome is known only when I7 reaches Execute (stage 4). The three instructions fetched after it (I8, I9, I10) are flushed, a penalty of 3 cycles.

\[ \begin{aligned} \text{cycles} &= (k - 1) + n + \text{penalty} \\ &= 4 + 11 + 3 = 18 \\ \text{time} &= 18 \times 8 = 144\ \text{ns} \end{aligned} \]

Running all 15 instructions without the branch would take (4 + 15) x 8 = 152 ns. 210 and 216 ns ignore pipelining, and 25 ns is a single instruction's latency without the common clock.

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