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Flip Flops and Latches Questions and Answers

1.

Identify whether the given statements are true or false.

1. T-flipflop is a digital circuit with two stable states.

2. For T = 0, the T-flipflop retains the same state at output.

Exam Year(s)

DSSSB AE - 2023,

Answer: A

Both statements are true. A T (toggle) flipflop is a bistable circuit: it has two stable states, which it holds until a clock pulse arrives. Its characteristic equation is \(Q_{next} = T \oplus Q\), so when \(T = 0\) the output is unchanged, and when \(T = 1\) the output toggles on the clock edge.


So the pair 1 true and 2 true is correct. The other options call one or both statements false, which contradicts the definition and the truth table. The answer is option A.

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2.

Which of the following is NOT a correct type of flipflop?

Exam Year(s)

DSSSB AE - 2023,

Answer: C

The standard flipflops are the SR (set reset) flipflop, the JK flipflop, the D (data or delay) flipflop and the T (toggle) flipflop. There is an SR flipflop, but there is no flipflop that has only a set input and is called an S flipflop, so that is the one that is not a correct type.


The JK flipflop removes the forbidden state of the SR type, the D flipflop copies its input to the output on the clock edge, and the T flipflop toggles when T is high. The answer is S flipflop, option C.

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3.

What is the name of the given flip flop circuit? If the present input state of flip flop is 1, What is its next output state? (E is always unity)

Flip flop made of four NAND gates with an inverter on the data input, an enable input E, and cross-coupled outputs Q and Q-bar

Exam Year(s)

DSSSB AE - 2023,

Answer: A

The circuit has a single data input, which is inverted to feed the second NAND gate, an enable input E, and a cross coupled pair of NAND gates giving Q and its complement. This is the gated D latch, a D flip flop: the output follows the data input while the enable is high. It is not a T flip flop, which would feed the output back to the input to toggle.


With \(E = 1\) the next state is equal to the data input, \(Q_{next} = D = 1\). So the circuit is a D flip flop and the next output state is 1. The answer is option A. A D flip flop never inverts the data, so the options with 0 for a D flip flop are wrong.

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4.

For a J-K flip flop, realised using NOR gate, what is the next output state, if present state input J = 1, K = 1 and present state output Q = 1?

Exam Year(s)

DSSSB AE - 2023,

Answer: C

The characteristic equation of a J-K flip flop is \(Q_{next} = J\bar{Q} + \bar{K}Q\). With \(J = K = 1\) and \(Q = 1\):


\[ Q_{next} = 1 \cdot 0 + 0 \cdot 1 = 0 \]


When both inputs are 1 the flip flop toggles, so a present output of 1 becomes 0 on the next clock, whether it is built from NAND or NOR gates. The options 1, 2 and 3 are not outputs that a flip flop can have after toggling from 1, since a bit is only 0 or 1, and 1 would mean no change. The answer is 0, option C.

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