Logic Families Questions and Answers

Answer: D

The assertion is false and the reason is true, so option (D) is right. The fan-out of a CMOS gate is high, not poor, because the input of a CMOS gate is a capacitor that draws almost no d.c. current, so one output can drive many inputs; the limit is the speed lost to the load capacitance. The reason, that the current driving capability of CMOS is poor, is true, since CMOS outputs supply less current than the bipolar TTL outputs. Option (A) and option (B) take the assertion as true. Option (C) takes the assertion as true and the reason as false, which reverses the facts.

Answer: A

The circuit is a TTL NAND gate with a totem pole output: a multi-emitter input transistor T1, a phase splitter T2, and the output pair T3 (with the diode D) and T4.

When all the inputs A and B are high, the base collector junction of T1 conducts, so current from the supply through the 4 kilohm resistor flows into the base of T2, which turns on and in turn drives T4 into saturation. The emitter voltage of T2 turns T4 on while the voltage at the collector of T2 falls too low to keep T3 and the diode conducting, so T3 is off. The output Z is pulled to ground through the saturated T4, so Z is low, logic 0.

That is the NAND gate action: the output is low only when all the inputs are high. The answer is 0, option A.

Answer: D

The correct equation is \(V_{NH} = V_{0H(Min)} - V_{1H(Min)}\), where the paper prints 0 and 1 for the O (output) and I (input) of \(V_{OH}\) and \(V_{IH}\).

The high-level noise margin is the gap between the lowest guaranteed high output of one gate and the lowest input the next gate still reads as high. Similarly the low-level margin is \(V_{NL} = V_{IL(Max)} - V_{OL(Max)}\).

Options A and B add the levels instead of subtracting them, and option C mixes the high-level output with the low-level margin. For standard TTL, for example, \(V_{OH(Min)} = 2.4\) V and \(V_{IH(Min)} = 2.0\) V give a high noise margin of 0.4 V.

Answer: C

In descending order of propagation delay the families are CMOS, TTL, ECL.

Standard CMOS (the 4000 series) is the slowest of the three, with delays of tens of nanoseconds, because its high-impedance transistors charge load capacitance slowly. Standard TTL is faster, about 10 ns per gate. ECL is the fastest, around 1 ns or less, because its transistors never saturate and so do not have to clear stored charge before switching.

The options beginning with ECL list the fastest family first, which is ascending order, and the option starting with TTL puts ECL in the middle.

Answer: A

The circuit works as an OR gate.

Both transistors are emitter followers sharing one emitter resistor R, with the output Y taken from the common emitters. If either input A or input B is high, that transistor conducts and pulls Y up to about one base-emitter drop below the input, so Y is high. Only when both inputs are low are both transistors off, and R pulls Y down to ground.

Y is high when A or B (or both) is high, which is the OR function. An AND gate would need the transistors in series. NOR and NAND need an inverting stage, with the output taken from a collector resistor, which this circuit does not have.

Answer: C

The key's answer is switch transistor logic.

In switch (pass-transistor) logic, MOS transistors are used directly as switches that steer signals, so a function such as a multiplexer or XOR can be built with far fewer transistors than with complementary gate structures. Fewer, smaller devices and less wiring per function give a higher integration density on the chip.

Transistor-transistor logic is a bipolar logic family, and bipolar devices with their resistors take much more area than MOS switches. 'Transistor buffer logic' and 'circuit level logic' are not design styles noted for density.

Answer: C

The typical invalid range is 0.8-2 volts.

For standard TTL logic, an input of 0.8 V or less is read as logic 0, and an input of 2.0 V or more as logic 1. Voltages between 0.8 V and 2.0 V are neither a valid 0 nor a valid 1, so they form the invalid (indeterminate) region.

The other ranges do not match these TTL thresholds.

Logic families define such a forbidden band so that noise on a signal near one level is not mistaken for the other level; inputs are expected to cross it quickly.

Answer: A

The logic families can be divided into 2 categories.

By the direction of current between a driving gate and the gate it drives, a family is either current sinking, where the driving output takes current in from the load input when it is LOW, as in TTL, or current sourcing, where the driving output supplies current to the load input.

Classifications by device type (RTL, DTL, TTL, ECL, CMOS and so on) give more groups, but that is a different basis from the flow of current between gates, so 3, 4 and 5 do not fit the question.

Answer: C

The voltage levels may be positive or negative.

Positive logic means only that the higher voltage stands for 1 and the lower for 0. It says nothing about the sign of either level. ECL, for example, works with a HIGH of about -0.9 V and a LOW of about -1.7 V and is still positive logic, because the less negative level is 1.

So the levels need not be positive, need not be negative, and need not be the 0 V and 5 V of TTL, which is one common choice rather than a requirement.

Answer: A

The matching is TTL with NAND, ECL with NOR and CMOS with the inverter, so the code is 1 2 3. TTL (transistor-transistor logic) has the NAND gate as its basic circuit. ECL (emitter-coupled logic) is built on a differential amplifier, whose basic circuit gives OR and NOR outputs, and CMOS is built from the complementary pair of transistors that make an inverter.

The other codes assign the NOR or the inverter to TTL, or NAND to CMOS, which does not agree with how each family is built.