Flip Flops and Latches Questions and Answers

Q: The race around condition in JK flipflop occurs when,

Race around occurs when J = 1, K = 1.With J = K = 1 a JK flip-flop toggles. In a level-triggered flip-flop, if the clock stays high longer than the propagation delay, the output keeps toggling again and again while the clock is high, so its final state is uncertain. This is the race around condition.J = 0, K = 0 holds the state, J = 1, K = 0 sets it and J = 0, K = 1 resets it; none of these makes the output change more than once, so none causes racing. The cure is a master-slave or edge-triggered flip-flop.

Q: To store N-bit word the number of Flip-Flops required is :

An N-bit word needs n Flip-Flops.A flip-flop is a one-bit memory element: it holds a single 0 or 1. A register that stores an n-bit word therefore needs one flip-flop per bit, n in all; an 8-bit register uses 8 flip-flops.\(2^{n}\) is the number of different values n flip-flops can hold (and the number of states of an n-bit counter), not the number of flip-flops. 2n and \(2^{n-1}\) have no such role: they would double or vastly overcount the storage needed.

Q: The main difference between JK and RS flip-flop is that :(a) JK flip-flop requires clock input(b) There is a feedback in JK flip-flop(c) JK flip-flop accepts both inputs as high(d) JK flip-flop is similar to D-flip flop

The keyed answer is a and c.The decisive difference (c) is that a JK flip-flop accepts J = K = 1: instead of the forbidden state of the RS flip-flop, it toggles. Statement (a) is the textbook contrast that a basic RS latch can work without a clock, whereas the JK flip-flop is a clocked device.Statement (b) does not distinguish the two, because an RS latch is itself built from two cross-coupled gates with feedback; the JK merely adds a further feedback path from the outputs to the input gates. Statement (d) is false: a JK flip-flop behaves like a D flip-flop only when K is tied to the complement of J. That rules out the options containing (b) or (d).

Q: In a D flip-flop output Q = Input D when :(a) The output is low(b) The output is high(c) Clock is enabled(d) Both reset and set input disabled

The keyed answer is (c) and (d).A D flip-flop copies its D input to Q on the active clock edge, so the clock must be enabled (c). Most practical D flip-flops also have asynchronous preset (set) and clear (reset) inputs, which override the clock; Q follows D only while both of these are inactive (d).The present state of the output, low (a) or high (b), has no bearing on whether D is transferred: the D flip-flop has no state-dependent input behaviour, unlike JK toggling. So the options including (a) or (b) are wrong, and (c) alone omits the condition on preset and clear.

Q: A 'D' Flip-Flop has the following data sheet : Information setup time = 5 nsec; hold time = 10 nsec; propagation time = 15 nsec.The output will change after the clock edge in a period of :

The output changes after 15 nsec.The propagation delay is the time from the active clock edge to the change at the output, and the data sheet gives it as 15 ns.The setup time (5 ns) is how long the D input must be stable before the clock edge, and the hold time (10 ns) is how long it must stay stable after it. Neither is the delay of the output. 20 ns adds the setup and propagation times, which has no meaning here.

Q: In the fission of U-235 nuclei, it is observed that the fission fragments decay by emission of negatively charged beta particles and attain state of stable nuclei.The reason for emission of negatively charged beta particles is that the fission fragments :

The fragments emit β− particles because they are rich in neutrons.U-235 has a neutron-to-proton ratio of about 1.55. The fission fragments, of mass number roughly 90 to 145, inherit nearly that ratio, but stable nuclei of that size have a ratio of only about 1.2 to 1.4. Each fragment therefore has too many neutrons, and it moves toward stability by a chain of β− decays, in each of which a neutron becomes a proton.Proton-rich nuclei decay by positron emission or electron capture, not β−. Prompt neutron emission does happen, but it only partly relieves the excess and is not the cause of beta decay, and spin has no bearing on the sign of the beta particle.

Identify whether the given statements are true or false.

1. T-flipflop is a digital circuit with two stable states.

2. For T = 0, the T-flipflop retains the same state at output.

A.1 - True; 2 - True
B.1 - False; 2 - False
C.1 - True; 2 - False
D.1 - False; 2 - True

Exam Year(s)

DSSSB AE - 2023,

Answer: A

Both statements are true. A T (toggle) flipflop is a bistable circuit: it has two stable states, which it holds until a clock pulse arrives. Its characteristic equation is \(Q_{next} = T \oplus Q\), so when \(T = 0\) the output is unchanged, and when \(T = 1\) the output toggles on the clock edge.

So the pair 1 true and 2 true is correct. The other options call one or both statements false, which contradicts the definition and the truth table. The answer is option A.

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Which of the following is NOT a correct type of flipflop?

A.JK flipflop
B.D flipflop
C.S flipflop
D.T flipflop

Exam Year(s)

DSSSB AE - 2023,

Answer: C

The standard flipflops are the SR (set reset) flipflop, the JK flipflop, the D (data or delay) flipflop and the T (toggle) flipflop. There is an SR flipflop, but there is no flipflop that has only a set input and is called an S flipflop, so that is the one that is not a correct type.

The JK flipflop removes the forbidden state of the SR type, the D flipflop copies its input to the output on the clock edge, and the T flipflop toggles when T is high. The answer is S flipflop, option C.

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What is the name of the given flip flop circuit? If the present input state of flip flop is 1, What is its next output state? (E is always unity)

Flip flop made of four NAND gates with an inverter on the data input, an enable input E, and cross-coupled outputs Q and Q-bar

A.D flip flop, 1
B.D flip flop, 0
C.T flip flop, 1
D.T flip flop, 0

Exam Year(s)

DSSSB AE - 2023,

Answer: A

The circuit has a single data input, which is inverted to feed the second NAND gate, an enable input E, and a cross coupled pair of NAND gates giving Q and its complement. This is the gated D latch, a D flip flop: the output follows the data input while the enable is high. It is not a T flip flop, which would feed the output back to the input to toggle.

With \(E = 1\) the next state is equal to the data input, \(Q_{next} = D = 1\). So the circuit is a D flip flop and the next output state is 1. The answer is option A. A D flip flop never inverts the data, so the options with 0 for a D flip flop are wrong.

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For a J-K flip flop, realised using NOR gate, what is the next output state, if present state input J = 1, K = 1 and present state output Q = 1?

Exam Year(s)

DSSSB AE - 2023,

Answer: C

The characteristic equation of a J-K flip flop is \(Q_{next} = J\bar{Q} + \bar{K}Q\). With \(J = K = 1\) and \(Q = 1\):

\[ Q_{next} = 1 \cdot 0 + 0 \cdot 1 = 0 \]

When both inputs are 1 the flip flop toggles, so a present output of 1 becomes 0 on the next clock, whether it is built from NAND or NOR gates. The options 1, 2 and 3 are not outputs that a flip flop can have after toggling from 1, since a bit is only 0 or 1, and 1 would mean no change. The answer is 0, option C.

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The race around condition in JK flipflop occurs when,

A.J = 0, K = 1
B.J = 1, K = 1
C.J = 0, K = 0
D.J = 1, K = 0

Exam Year(s)

RSMSSB JE - 2025, RSMSSB - 2025,

Answer: B

Race around occurs when J = 1, K = 1.

With J = K = 1 a JK flip-flop toggles. In a level-triggered flip-flop, if the clock stays high longer than the propagation delay, the output keeps toggling again and again while the clock is high, so its final state is uncertain. This is the race around condition.

J = 0, K = 0 holds the state, J = 1, K = 0 sets it and J = 0, K = 1 resets it; none of these makes the output change more than once, so none causes racing. The cure is a master-slave or edge-triggered flip-flop.

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To store N-bit word the number of Flip-Flops required is :

A.\(2^{n}\) Flip-Flops
B.2n Flip-Flops
C.n Flip-Flops
D.\(2^{n-1}\) Flip-Flops

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: C

An N-bit word needs n Flip-Flops.

A flip-flop is a one-bit memory element: it holds a single 0 or 1. A register that stores an n-bit word therefore needs one flip-flop per bit, n in all; an 8-bit register uses 8 flip-flops.

\(2^{n}\) is the number of different values n flip-flops can hold (and the number of states of an n-bit counter), not the number of flip-flops. 2n and \(2^{n-1}\) have no such role: they would double or vastly overcount the storage needed.

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The main difference between JK and RS flip-flop is that :

(a) JK flip-flop requires clock input
(b) There is a feedback in JK flip-flop
(c) JK flip-flop accepts both inputs as high
(d) JK flip-flop is similar to D-flip flop

A.a and b
B.b only
C.a and c
D.b and d

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: C

The keyed answer is a and c.

The decisive difference (c) is that a JK flip-flop accepts J = K = 1: instead of the forbidden state of the RS flip-flop, it toggles. Statement (a) is the textbook contrast that a basic RS latch can work without a clock, whereas the JK flip-flop is a clocked device.

Statement (b) does not distinguish the two, because an RS latch is itself built from two cross-coupled gates with feedback; the JK merely adds a further feedback path from the outputs to the input gates. Statement (d) is false: a JK flip-flop behaves like a D flip-flop only when K is tied to the complement of J. That rules out the options containing (b) or (d).

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In a D flip-flop output Q = Input D when :

(a) The output is low
(b) The output is high
(c) Clock is enabled
(d) Both reset and set input disabled

A.(c)
B.(a) and (b)
C.(a) and (c)
D.(c) and (d)

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: D

The keyed answer is (c) and (d).

A D flip-flop copies its D input to Q on the active clock edge, so the clock must be enabled (c). Most practical D flip-flops also have asynchronous preset (set) and clear (reset) inputs, which override the clock; Q follows D only while both of these are inactive (d).

The present state of the output, low (a) or high (b), has no bearing on whether D is transferred: the D flip-flop has no state-dependent input behaviour, unlike JK toggling. So the options including (a) or (b) are wrong, and (c) alone omits the condition on preset and clear.

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A 'D' Flip-Flop has the following data sheet : Information setup time = 5 nsec; hold time = 10 nsec; propagation time = 15 nsec.

The output will change after the clock edge in a period of :

A.5 nsec
B.10 nsec
C.15 nsec
D.20 nsec

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: C

The output changes after 15 nsec.

The propagation delay is the time from the active clock edge to the change at the output, and the data sheet gives it as 15 ns.

The setup time (5 ns) is how long the D input must be stable before the clock edge, and the hold time (10 ns) is how long it must stay stable after it. Neither is the delay of the output. 20 ns adds the setup and propagation times, which has no meaning here.

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10.

In the fission of U-235 nuclei, it is observed that the fission fragments decay by emission of negatively charged beta particles and attain state of stable nuclei.

The reason for emission of negatively charged beta particles is that the fission fragments :

A.have different mass numbers and high values of spins
B.are rich in protons
C.emit prompt neutrons
D.are rich in neutrons

Exam Year(s)

MH SET - 2018, SET Exam - 2018,

Answer: D

The fragments emit β⁻ particles because they are rich in neutrons.

U-235 has a neutron-to-proton ratio of about 1.55. The fission fragments, of mass number roughly 90 to 145, inherit nearly that ratio, but stable nuclei of that size have a ratio of only about 1.2 to 1.4. Each fragment therefore has too many neutrons, and it moves toward stability by a chain of β⁻ decays, in each of which a neutron becomes a proton.

Proton-rich nuclei decay by positron emission or electron capture, not β⁻. Prompt neutron emission does happen, but it only partly relieves the excess and is not the cause of beta decay, and spin has no bearing on the sign of the beta particle.

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