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Instruction Set Architecture Questions and Answers

11.

XLAT instruction in assembly is used to :

Exam Year(s)

MH SET - 2021, SET Exam - 2021,

Answer: B

XLAT is used to perform character conversions.

XLAT (translate) on the 8086 replaces the byte in AL with the byte found in a lookup table at address BX + AL: AL is used as an index into a table whose start is in BX. It is used for code conversion, for example converting a character from one code to another or a digit to its seven-segment pattern, one byte at a time.

It is not a string instruction (those are MOVS, CMPS, SCAS, LODS and STOS) and does not process a whole string. Performance is not its purpose, and 'none of the above' is wrong because its purpose is listed.

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12.

Stack Pointer Register (SP) in x86 architecture is generally used to .................. .

Exam Year(s)

MH SET - 2024, SET Exam - 2024,

Answer: B

The stack pointer is used to point to the top of the stack.

In x86, SP (ESP or RSP) holds the address of the current top of the stack. PUSH decrements it and stores a value there, and POP reads the value and increments it; CALL and RET use it for return addresses.

The base of the current stack frame is held by a different register, BP (EBP or RBP). SP's role does not switch with the opcode or the addressing mode.

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Answer: B

The key gives (B) to provide a high-level abstraction of hardware for the programmer.

Assembly language replaces the binary codes of machine language with mnemonics such as ADD and MOV and with symbolic names for registers and addresses. In that sense it gives the programmer a more readable, symbolic view of the hardware than raw machine code, while staying close to it.

Treat the wording of B as the key's: assembly is normally called a low-level language, so "high-level" is relative to machine code only. The other options are plainly wrong. Assembly is not a natural language (A). The computer cannot execute assembly text directly: an assembler must first translate it to machine code (C). And assembly is specific to one processor family, so it does not run on different platforms (D).

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14.

Which of the following statements is true with respect to RISC architecture in comparison with CISC architecture ?

Exam Year(s)

MH SET - 2025, SET Exam - 2025,

Answer: C

In RISC instructions are generally of fixed length.

RISC designs use a small set of simple instructions of uniform length and format, with few addressing modes, so they can be decoded quickly and pipelined efficiently, usually one instruction per clock cycle.

A larger instruction set, more addressing modes and complex instructions are all characteristics of CISC, which uses variable-length instructions that may take many cycles. Each of the other options therefore describes CISC, not RISC.

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15.

In a processor that uses a full-descending stack organization, what happens during a PUSH operation ?

Exam Year(s)

Tripura Public Service Commission - 2026,

Answer: A

In a full-descending stack, PUSH does decrement SP, then write data.

'Descending' means the stack grows towards lower addresses. 'Full' means the stack pointer points at the last item actually pushed, the top occupied location. To push, the processor must first move SP down to the next free location and then store the data there, so the order is decrement, then write (ARM's STMFD, used by the standard ARM calling convention, works this way).

Write, then decrement describes an empty descending stack, where SP points to the next free slot. The two increment options describe ascending stacks, which grow towards higher addresses.

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16.

What is the main reason for separating the opcode field and addressing mode field in instruction formats ?

Exam Year(s)

Tripura Public Service Commission - 2026,

Answer: A

The main reason is to increase orthogonality of the instruction set.

When the opcode (what to do) and the addressing mode (where the operands are) sit in separate fields, any operation can be combined with any addressing mode. That independence is called orthogonality. It makes the instruction set regular and easier for programmers and compilers to use, since there are no special cases where one operation forbids a mode another allows (the VAX and Motorola 68000 were noted examples).

Separate fields do not in themselves minimise instruction length; they often lengthen it. They do not chiefly simplify the control unit, and they have nothing to do with allowing variable-length opcodes.

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17.

Which instruction in the 8085 microprocessor is used to stop the execution of the program ?

Exam Year(s)

Tripura Public Service Commission - 2025,

Answer: B

The instruction is HALT (written HLT in 8085 assembly).

HLT halts the 8085: the processor stops executing instructions and waits in a halt state until an interrupt or a reset occurs.

JMP transfers control to another address, NOP does nothing for one instruction and moves on, and RET returns from a subroutine. None of them stops the program.

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18.

In the 8085 microprocessor, what happens when the instruction "HILT" is executed ?

Exam Year(s)

Tripura Public Service Commission - 2025,

Answer: A

The key gives The microprocessor halts execution and stops the clock.

The paper's 'HILT' is the 8085's HLT instruction. On HLT, the processor finishes the current instruction and stops fetching and executing further instructions, entering a halt state until an interrupt or reset. (Strictly, the clock oscillator keeps running and the CPU simply idles; the option's 'stops the clock' is a loose description of that halt.)

Clearing the accumulator (XRA A), loading memory (STA, MOV M) and returning from a subroutine (RET) are done by other instructions.

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19.

Which of the following is NOT a characteristic of RISC architecture ?

Exam Year(s)

Tripura Public Service Commission - 2026,

Answer: C

The feature that is not RISC is complex addressing modes.

RISC (Reduced Instruction Set Computer) designs keep a small set of simple, fixed-length instructions with only a few simple addressing modes, so that each instruction can finish in about one cycle and pipeline easily. Complex addressing modes are a mark of CISC designs such as x86 and the VAX.

The other three are RISC features. The simple instructions can be decoded by a hardwired control unit, without microcode. In a load-store architecture only load and store instructions touch memory, and all arithmetic works on registers.

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20.

The following code segment is executed on a processor which allows only register operands in its instructions. Each instruction can have at most two source operands and one destination operand. Assume that all variables are dead after this code segment.

c = a + b;
d = c * a;
e = c + a;
x = c * c;
if(x > a) {
  y = a * a;
}
else {
  d = d*d;
  e = e * e;
}

Suppose the instruction set architecture of the processor has only two registers. The only allowed compiler optimization is code motion, which moves statements from one place to another while preserving correctness. What is the minimum number of spills to memory in the compiled code ?

Exam Year(s)

Tripura Public Service Commission - 2025,

Answer: B

The minimum number of spills is 1.

Two points settle it. First, a and b are never reassigned, so they can be reloaded from their memory locations whenever needed; only storing a value computed in the code counts as a spill. Second, code motion lets d = c * a and e = c + a move into the else branch, the only place their values are used.

At least one spill. At the test x > a, both x and a must be in the two registers, and c is still needed afterwards to compute d and e in the else branch. Three values need to survive with two registers, so c must be stored to memory once.

One is enough. R1 = a, R2 = b; R2 = a + b (c); store c (the spill); R2 = c * c (x); compare R2 with R1. In the if branch, y = a * a uses R1. In the else branch, reload c into R2, compute d = c * a into R1, then d = d * d; reload a into R1, compute e = c + a into R2, then e = e * e.

So 0 is impossible and 2 or 3 are more than needed.

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